A Digital to Time Converter with Fully Digital Calibration Scheme for Ultra-Low Power ADPLL in 40 nm CMOS

机译：一种带有全数字校准方案的数字转换器，用于40 nm CMOS中的超低功耗ADPLL

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In this paper, a digital-to-time converter (DTC) assisting a time-to-digital converter (TDC) as a fractional phase error detector in an ultra-low power ADPLL is proposed and demonstrated in 40nm CMOS. A phase prediction algorithm via the assistance of the DTC reduces the required TDC range, thus saving substantial power. Additionally, a fully digital calibration algorithm is presented and proved to validate the whole ADPLL system and improve the DTC linearity. At 1 V supply voltage, the measured time resolution of the DTC is 22 ps. The TDC resolution is also indirectly measured with a closed-loop 2.4 GHz ADPLL, where -95.3 dBc/Hz in-band phase noise corresponds to a worst-case TDC resolution of 22 ps.

机译：本文提出了一种数字转换器（DTC），其辅助时间转换器（TDC）作为超低功率ADPLL中的分数相位误差检测器，并在40nm CMOS中演示。通过DTC的帮助的相位预测算法减少了所需的TDC范围，从而节省了大量功率。此外，介绍了完全数字校准算法，并证明验证整个ADPLL系统并提高DTC线性度。在1 V电源电压下，DTC的测量时间分辨率为22 ps。 TDC分辨率也用闭环2.4GHz ADPLL间接测量，其中-95.3 DBC / Hz带内噪声对应于22 PS的最坏情况TDC分辨率。

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《IEEE International Symposium on Circuits and Systems》|2015年||共4页
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Bindi Wang; Yao-Hong Liu; Pieter Harpe; Johan van den Heuvel; Bo Liu; Hao Gao; Robert Bogdan Staszewski;
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中图分类电工技术;
关键词
Digital-to-time converter(DTC); time-to-digital converter (TDC); ADPLL; ultra-low power; CMOS;

机译：数待时间转换器（DTC）;时间到数字转换器（TDC）;ADPLL;超低功率;CMOS;

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专利

1. A 360-fs-Time-Resolution 7-bit Stochastic Time-to-Digital Converter With Linearity Calibration Using Dual Time Offset Arbiters in 65-nm CMOS [J] . Chung Hayun, Hyun Minji, Kim Jungwon IEEE Journal of Solid-State Circuits . 2021,第3期

机译：360-FS - 时间分辨率7位随机时间转换器，具有线性校准，在65-nm cmos中使用双重时间偏移仲裁器
2. A 15-b 40-MS/s CMOS Pipelined Analog-to-Digital Converter With Digital Background Calibration [J] . Hung-Chih Liu, Zwei-Mei Lee, Jieh-Tsorng Wu IEEE Journal of Solid-State Circuits . 2005,第5期

机译：具有数字背景校准功能的15b 40-MS / s CMOS流水线模数转换器
3. An Ultra-Low Power 1.7-2.7 GHz Fractional-N Sub-Sampling Digital Frequency Synthesizer and Modulator for IoT Applications in 40 nm CMOS [J] . Yao-Hong Liu, Johan Van Den Heuvel, Takashi Kuramochi, Circuits and Systems I: Regular Papers, IEEE Transactions on . 2017,第5期

机译：用于40 nm CMOS的物联网应用的超低功耗1.7-2.7 GHz小数N分采样数字频率合成器和调制器
4. A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS [C] . Wang Bindi, Liu Yao-Hong, Harpe Pieter, IEEE International Symposium on Circuits and Systems . 2015

机译：具有全数字校准方案的数模转换器，用于40 nm CMOS中的超低功耗ADPLL
5. Design of a wideband low-power continuous-time sigma-delta (SigmaDelta) analog-to-digital converter (ADC) in 90nm CMOS technology. [D] . Chen, Fang. 2009

机译：采用90nm CMOS技术的宽带低功耗连续时间sigma-delta（SigmaDelta）模数转换器（ADC）的设计。
6. An Accurate Timing Alignment Method with Time-to-Digital Converter Linearity Calibration for High-Resolution TOF PET [O] . Hongdi Li, Chao Wang, Shaohui An, -1

机译：具有高分辨率TOF PET的具有时间数字转换器线性校准的精确定时对准方法
7. A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS [O] . Wang, Bindi, Liu, Yao-Hong, Harpe, Pieter, 2015

机译：具有全数字校准方案的数模转换器，用于40 nm CMOS中的超低功耗ADPLL

A Digital to Time Converter with Fully Digital Calibration Scheme for Ultra-Low Power ADPLL in 40 nm CMOS

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