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Perils of power prediction in early power-integrity analysis

机译:早期功率完整性分析中功率预测的风险

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Early power integrity and peak power analyses for multi-million gate system on chip (SoC) in advanced technology nodes pose significant methodology definition and implementation challenges. Typically in a SoC, processors and other high performance IPs are dominant contributors to peak power and power integrity issues. To get an early look ahead of potential power integrity issues and to estimate peak di/dt issues in the SoC, it is always desired to analyze potential issues early and address before a silicon failure. This paper presents an overview of implementation challenges faced in RTL based power for predictive power analysis and analyzing peak di/dt issues ahead of time in the context of TI C66× DSP core based multicore SoC.
机译:先进技术节点中数以百万计的片上系统(SoC)的早期功率完整性和峰值功率分析带来了重大的方法学定义和实施挑战。通常,在SoC中,处理器和其他高性能IP是导致峰值功率和功率完整性问题的主要因素。为了及早发现潜在的电源完整性问题并估计SoC中的峰值di / dt问题,始终需要尽早分析潜在问题并在芯片故障之前解决。本文概述了在基于TI C66x DSP内核的多核SoC中,用于预测功率分析和提前分析峰值di / dt问题的基于RTL的功率面临的实施挑战。

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