This paper describes a hybrid frequency/phase-locked loop (F/PLL) in which a PLL operates as a nested digitally-controlled oscillator (DCO). The nested DCO based on the wideband PLL not only offers a constant gain but also enables low noise clock generation even with a very low reference frequency. A digital FLL with a 1-bit AZ frequency detector (FD) is designed as a main loop to avoid having a linear time-to-digital converter (TDC). A prototype fractional-N F/PLL is implemented in 65nm CMOS. The proposed F/PLL achieves an in-band noise of ???90dBc/Hz at 1.5GHz output with a 15kHz reference clock and a 60MHz system clock, consuming 9.2mW from a 1V supply.
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