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首页> 外文会议>IEEE MTT-S International Microwave Symposium >A 90 nm CMOS low phase noise sub-harmonically injection-locked voltage-controlled oscillator with FLL self-alignment technique
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A 90 nm CMOS low phase noise sub-harmonically injection-locked voltage-controlled oscillator with FLL self-alignment technique

机译：具有FLL自对准技术的90 nm CMOS低相位噪声亚谐波注入锁定压控振荡器

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摘要

An innovative low phase noise sub-harmonically injection-locked voltage-controlled oscillator (SILVCO) with frequency-locked loop (FLL) self-alignment technique is presented in this paper using 90 nm CMOS process. To overcome the issue of narrow locking range, the control voltage of the SILVCO is adaptively adjusted using the FLL technique to refer to the sub-harmonic input frequency. This work demonstrates excellent robustness over temperature variation from 10°C to 70° C. Under the locking condition of the SILVCO with FLL, the measured minimum phase noise is -130.4 dBc/Hz at 1 MHz offset, the measured minimum jitter integrated from 50 kHz to 80 MHz is lower than 30.5 fs, and the output frequency is from 9.9 to 10.4 GHz. The circuit performance can be compared to the advanced CMOS low phase noise clock generators.
机译：本文采用90 nm CMOS工艺，提出了一种创新的具有相位锁定环（FLL）自对准技术的低相位噪声亚谐波注入锁定压控振荡器（SILVCO）。为了克服窄锁定范围的问题，可使用FLL技术自适应调整SILVCO的控制电压，以参考次谐波输入频率。这项工作证明了在从10°C到70°C的温度变化范围内具有出色的鲁棒性。在带FLL的SILVCO锁定条件下，在1 MHz偏移下测得的最小相位噪声为-130.4 dBc / Hz，从50 kHz至80 MHz低于30.5 fs，输出频率为9.9至10.4 GHz。电路性能可以与先进的CMOS低相位噪声时钟发生器相提并论。

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