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首页> 外文会议>IEEE International Conference on Electron Devices and Solid-State Circuits >Systolic array based VLSI architecture for high throughput 2-D discrete wavelet transform
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Systolic array based VLSI architecture for high throughput 2-D discrete wavelet transform

机译：用于高通量二维离散小波变换的基于脉动阵列的VLSI架构

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A new data scan method is proposed for 2-D discrete wavelet transform to access more pixels in one clock cycle. Unlike existing stripe based method, in our design adjacent even and odd rows are read and processed at the same time. The concurrent output from even and odd row transform units inherently eliminate the data sequencing between row transform and column transform. Thus the transposition memory is not needed any more. For the row transform unit, a novel systolic array structure is constructed with pipeline technique employed to reduce the critical path delay. Without too many additional registers, the improved critical path delay of Tm is superior to most of the stripe based designs. For the column transform unit, a conventional lifting based two-input/two-output structure is adopted. Theoretical analysis shows that this design is suitable for applications which have demanding throughput rate and high operation frequency requirements. Synthesis results in UMC 130nm process show that the Area Delay Product is 23%, 27.3% and 29.6% better than the best existing stripe based structure for S=2, 4 and 8.
机译：提出了一种用于二维离散小波变换的新数据扫描方法，以在一个时钟周期内访问更多像素。与现有的基于条带的方法不同，在我们的设计中，相邻的偶数和奇数行同时读取和处理。来自偶数和奇数行变换单元的并发输出本质上消除了行变换和列变换之间的数据排序。因此，不再需要转置存储器。对于行变换单元，采用流水线技术构造了一种新颖的脉动阵列结构，以减少关键路径延迟。由于没有太多的额外寄存器，改进的Tm关键路径延迟优于大多数基于条带的设计。对于列变换单元，采用常规的基于提升的二输入二输出结构。理论分析表明，该设计适合具有较高吞吐速率和较高工作频率要求的应用。在UMC 130nm工艺中的合成结果表明，对于S = 2、4和8，面积延迟乘积比现有的最佳基于条纹的结构好23％，27.3％和29.6％。

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