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Proposed architecture for an FPGA configuration for a payload module computer

机译：负载模块计算机的FPGA配置的建议架构

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This paper introduces an Field Programmable Gate Array (FPGA) configuration architecture for the use on an FPGA based Payload Module Computer (PMC) on a satellite. This architecture was developed during the small satellite project ¿¿¿Flying Laptop¿¿¿. The challenge was to have a short development time to enable early testing of the payloads and the interfaces to the On-Board Computer (OBC), but simultaneously retaining the ability to extend the configuration with different data routing and data processing algorithms. As a result the configuration is divided into two layers. In the first layer, the controlling layer, commands and telemetry is exchanged between the OBC and the payloads. At this layer the Payload Module Computer (PMC) mainly functions as a router. The second layer is called the data handling layer. Within this layer data is transferred from any data source to any data sink in pipelining mode. Using an FPGA this routing happens in parallel for as many payloads as desired. The routing of payload data, as well as the enabling and disabling of data processing cores, is configurable during runtime. All payload handlers, as well as data processing cores, have a straightforward and standardized interface. This enables an easy exchange of future data processing cores or even an addition or exchange of payloads. With the proposed architecture a foundation for the development of FPGA configurations for PMCs is established. Utilizing this architecture introduces a way to test payloads early without the need to write extra code for testing. The customizable data routing during run time leads to easier testing of new cores and handlers, due to the easy usage of debug output ports. Also in case of a damaged memory chip the data can easily be rerouted to a healthy chip. Adding or exchanging multiple data processing cores or payloads at any time is easy, which results in a flexible architecture.
机译：本文介绍了一种现场可编程门阵列（FPGA）配置架构，该架构可在卫星上基于FPGA的有效载荷模块计算机（PMC）上使用。该架构是在小型卫星项目“飞笔记本电脑”中开发的。面临的挑战是开发时间短，可以对有效载荷和车载计算机（OBC）的接口进行早期测试，但同时要保留使用不同的数据路由和数据处理算法来扩展配置的能力。结果，配置分为两层。在第一层中，控制层，命令和遥测在OBC和有效载荷之间交换。在这一层，有效负载模块计算机（PMC）主要充当路由器。第二层称为数据处理层。在这一层中，数据以流水线模式从任何数据源传输到任何数据接收器。使用FPGA，这种路由并行发生，可实现所需数量的有效负载。有效负载数据的路由以及数据处理核心的启用和禁用可在运行时进行配置。所有有效负载处理程序以及数据处理核心均具有简单，标准化的界面。这样可以轻松交换未来的数据处理核心，甚至可以增加或交换有效负载。利用所提出的架构，为开发用于PMC的FPGA配置奠定了基础。利用这种体系结构引入了一种无需提前编写额外代码即可进行测试的早期测试有效负载的方法。由于易于使用调试输出端口，因此在运行时可自定义的数据路由可简化对新内核和处理程序的测试。同样，在存储芯片损坏的情况下，可以轻松地将数据重新路由到正常运行的芯片。随时添加或交换多个数据处理核心或有效负载很容易，这导致了灵活的体系结构。

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