• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文会议>International Conference on Inventive Computation Technologies >Pipelined and folded energy — Efficientfft processors
【24h】

Pipelined and folded energy — Efficientfft processors

机译：流水线和折叠式能源—高效处理器

获取原文
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

This paper describes the design of a low area, power efficient and high performance Fast Fourier Transform (FFT) processor using an energy efficient adder architecture and a mod-ified booth multiplier architecture in place of the ordinary CMOS logic adder circuit and multiplier circuit, respectively. Variable supply voltage (VSV) scaling was implemented in the processor which is an efficient way to reduce energy consumption by lowering the operating voltage and determining the non-critical path of the processor simultaneously. Low power was obtained using hybrid robust adder which uses pass transistor logic and constant voltage scaling. High performance was achieved by using pipelining and parallel processing whereas low area was attained by using the folding architecture. 90nm technology architecture was designed and used to verify the functionality of the proposed system showing the power consumption and computational time in Cadence.
机译：本文介绍了分别使用普通的CMOS逻辑加法器电路和乘法器电路，采用节能型加法器架构和改进的Booth乘法器架构设计的低面积，低功耗，高性能和快速傅立叶变换（FFT）处理器的设计。 。在处理器中实现了可变电源电压（VSV）缩放，这是通过降低工作电压并同时确定处理器的非关键路径来降低能耗的有效方法。使用混合鲁棒加法器获得了低功率，该混合鲁棒加法器使用传输晶体管逻辑和恒定电压定标。使用流水线和并行处理可实现高性能，而使用折叠结构则可实现较小的面积。设计了90nm技术架构，并将其用于验证所提出系统的功能，从而显示Cadence中的功耗和计算时间。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号