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An efficient voltage and frequency division method for multiprecision multiplier on FPGA

机译：FPGA上一种高效的高精度倍频乘法器

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In this paper, an efficient Dynamic voltage and frequency scaling (DVFS) for multi precision multiplier on reconfigurable FPGA is proposed. This paper is focusing on implementation of multiplier which works on runtime data with lower supply and clock frequency. Multipliers plays important role in arithmetic operations and it is power consuming part of circuit. This system is designed to address the issue of excess power consumption at lower workload. Dynamic system is developed for effective use of reconfigurable hardware and to address the power challenge. Range detection is the first step for making system dynamic once range is detected it generates control signal to frequency scaling unit, voltage scaling unit, and multiplication. In the Multiplication reversible gate as multiplier and Kogge-stone adder is used which results in efficient use of LUT's and delays as compared with previous scheme. To maintain performance trend in the age of runtime changing hardware configuration, it is beneficial to implement Multiprecision multiplier (MP) multiplier in modern XILINX as part of an FPGA. Experimental result shows that implementation of DVFS for multiplier block is on FPGA and it is offering good performance at low power supply voltage 3.3V to 1.25V and frequency 32MHz to 8MHz.
机译：本文提出了一种可重构FPGA上用于多精度乘法器的高效动态电压和频率缩放（DVFS）。本文的重点是乘法器的实现，该乘法器适用于具有较低电源和时钟频率的运行时数据。乘法器在算术运算中起着重要作用，它是电路的功耗部分。该系统旨在解决工作负载较低时功耗过大的问题。开发动态系统是为了有效利用可重新配置的硬件并解决电源挑战。范围检测是使系统动态化的第一步，一旦检测到范围，它就会生成控制信号到频率缩放单元，电压缩放单元和乘法。在乘法中，可逆门用作乘法器和科格斯通加法器，与以前的方案相比，可以有效地利用LUT和延迟。为了在运行时更改硬件配置的时代保持性能趋势，在现代XILINX中作为FPGA的一部分实现多精度乘法器（MP）乘法器是有益的。实验结果表明，用于DVFS的乘法器模块是在FPGA上实现的，并且在3.3V至1.25V的低电源电压和32MHz至8MHz的频率下具有良好的性能。

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