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首页> 外文会议>IEEE/ACM International Conference on Computer-Aided Design >State retention for power gated design with non-uniform multi-bit retention latches
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State retention for power gated design with non-uniform multi-bit retention latches

机译：具有非均匀多位保持锁存器的功率门控设计的状态保持

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摘要

Retention registers/latches are commonly applied to power-gated circuits for state retention during the sleep mode. Recent studies have shown that applying uniform multi-bit retention registers (MBRRs) can reduce the storage size, and hence save more chip area and leakage power compared with single-bit retention registers. In this paper, a new problem formulation of power-gated circuit optimization with nonuniform MBRRs is studied for achieving even more storage saving and higher storage utilization. An ILP-based approach is proposed to effectively explore different combinations of nonuniform MBRR replacement. Experiment results show that the proposed approach can reduce 36% storage size, compared with the state-of-the-art uniform MBRR replacement, while achieving 100% storage utilization.
机译：保持寄存器/锁存器通常应用于电源门控电路，以在睡眠模式下保持状态。最近的研究表明，与单一位保留寄存器相比，应用统一的多位保留寄存器（MBRR）可以减小存储大小，从而节省更多的芯片面积和泄漏功率。本文研究了具有不均匀MBRR的功率门控电路优化的新问题公式，以实现更多的存储节省和更高的存储利用率。提出了一种基于ILP的方法来有效地探索非均匀MBRR替换的不同组合。实验结果表明，与最新的统一MBRR替换相比，该方法可减少36％的存储大小，同时实现100％的存储利用率。

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