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首页> 外文会议>IEEE International Solid- State Circuits Conference >A −242dB FOM and −75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC
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A −242dB FOM and −75dBc-reference-spur ring-DCO-based all-digital PLL using a fast phase-error correction technique and a low-power optimal-threshold TDC

机译：采用快速相位误差校正技术和低功耗最佳阈值TDC的-242dB FOM和-75dBc参考杂散环DCO基全数字PLL

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To improve efficiency in the use of silicon, there have been many efforts to develop ring-oscillator-based clock generators with low jitter. A PLL using a fast phase-error correction (FPEC) technique [1] is one promising architecture. By emulating the phase-realignment mechanism of an injection-locked clock multiplier (ILCM), the FPEC PLL can achieve ultra-low jitter that is almost comparable to that of ILCMs. In addition, since the FPEC PLL has an integrator in its transfer function, it can also achieve a low reference spur and a high multiplication factor (N), which is different from ILCMs. However, the FPEC PLL of an analog implementation in [1] has difficulty maintaining optimal loop characteristics, which vary easily due to PVT variations or a change in the output frequency. To facilitate the calibration of loop characteristics, the FPEC can be implemented in an all-digital PLL (ADPLL), increasing the control word of a DCO, DFCW, in a very short duration, TFPEC, as shown in Fig. 25.4.1. Since the FPEC technique can rapidly remove the accumulated jitter of the DCO from the previous reference period, fREF, the variance of the output jitter, VAR[JOUT](f), becomes saw-tooth-shaped along with the accumulating jitter. In a conventional ADPLL, the accumulated jitter is removed gradually over TREF, so the variance of the jitter is nearly constant [2]. This difference enables the FPEC ADPLL to have much lower RMS jitter, σRMS. However, the FPEC ADPLL is limited in its ability to achieve extremely low jitter, i.e., it cannot reduce σRMSas much as analog FPEC PLLs can. This is because typical ADPLL TDCs provides less precise information regarding the oscillator jitter than a PD does in analog PLLs. When it detects a timing error, τerr, a TDC generates a digitized value, DTDC; thus, the amount of error to be corrected becomes rather than τerr. This results in a quantization error, τq, thereby increasing σrms. To minimize τq(or E[τq2]), the resolution of a TDC must be improved significantly to a level at which the quantity of jitter can be distinguished, but this is difficult when a typical CMOS process is used. Even if the design itself were possible, additional power would be required to generate many evenly spaced time thresholds.
机译：为了提高硅的使用效率，已经进行了许多努力来开发具有低抖动的基于环形振荡器的时钟发生器。使用快速相位误差校正（FPEC）技术的PLL [1]是一种很有前途的架构。通过仿真注入锁定时钟乘法器（ILCM）的相位重新排列机制，FPEC PLL可以实现几乎与ILCM相当的超低抖动。此外，由于FPEC PLL在传递函数中具有积分器，因此它还可以实现低基准杂散和高倍数（N），这与ILCM有所不同。然而，文献[1]中的模拟实现的FPEC PLL难以维持最佳环路特性，该环路特性容易因PVT变化或输出频率变化而变化。为了简化环路特性的校准，可以在全数字PLL（ADPLL）中实现FPEC，从而增加了DCO，D的控制字。 FCW ，在很短的时间内，T FPEC ，如图25.4.1所示。由于FPEC技术可以快速消除上一个参考周期内DCO的累积抖动，因此f REF ，输出抖动的方差VAR [J OUT ]（f），随着累积的抖动而变成锯齿形。在传统的ADPLL中，累积的抖动会在T上逐渐消除 REF ，因此抖动的变化几乎是恒定的[2]。这种差异使FPEC ADPLL具有更低的RMS抖动σ RMS 。但是，FPEC ADPLL实现极低抖动的能力受到限制，即，它无法减小σ RMS 尽可能多的模拟FPEC PLL。这是因为与模拟PLL中的PD相比，典型的ADPLL TDC提供的关于振荡器抖动的信息不够精确。当它检测到定时误差时，τ err ，TDC生成数字化值D TDC ;因此，要校正的误差量变为τ，而不是τ err 。这导致量化误差τ q ，从而增加σ rms 。最小化τ q （或E [τ q 2 ]），必须将TDC的分辨率显着提高到可以区分抖动量的水平，但这在使用典型的CMOS工艺时很困难。即使设计本身是可行的，也将需要额外的功率来生成许多均匀间隔的时间阈值。

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