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Constructing a Metrology Sampling Framework for In-line Inspection in Semiconductor Fabrication

机译:构建用于半导体制造在线检测的计量采样框架

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Due to the shrinking IC device geometries and increasing interconnect layers, process complexity has been rapidly increasing and leads to higher manufacturing costs and longer cycle time. Thus, in-line metrology is set at various steps to inspect the wafer in real time, which often causes lots of inspection costs and also increases cycle time. This study aims to develop a framework for in-line metrology sampling to determine the optimal sampling strategy in the light of different objectives to reduce extra cost and cycle time.
机译:由于IC器件几何形状和增加互连层,过程复杂性已经迅速增加并且导致更高的制造成本和更长的循环时间。因此,在线计量以各个步骤设定,以实时检查晶片,这通常会导致大量检查成本并且还增加循环时间。本研究旨在开发一项框架,用于在线测量采样,以确定鉴于不同目标的最佳采样策略,以减少额外的成本和循环时间。

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