Channelization RAID storage system requests multichannel data transmission and high transmission bandwidth. We design a data caching system which is inserted between fore-end data source interface and the back-end RAID interface on a FPGA implementation. The caching system uses DDR3 as the external memory because of its large storage capacity and high storage rate. It uses a special channel management system and only needs three clock cycles to complete the read-write scheduling of different channels. The caching system provides the AXI4-Lite interface, so it can be dynamically configured by the AXI4-Lite bus. After testing, the caching system can satisfy the request of multichannel storage task.
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