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首页> 外文会议>IEEE International Conference on Integrated Circuits, Technologies and Applications >Enhanced FIR-embedded noise reduction method with hybrid phase detection for semidigital fractional-N phase-locked loops
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Enhanced FIR-embedded noise reduction method with hybrid phase detection for semidigital fractional-N phase-locked loops

机译：半数字分数-N锁相环的具有混合相位检测的增强型FIR嵌入式降噪方法

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摘要

This paper describes a phase noise reduction method with hybrid phase detection in the design of semidigital ΔΣ phase-locked loops (PLLs) that employ a finite impulse response (FIR) filtering technique for quantization noise reduction. A static phase offset problem is addressed and the use of a hybrid phase detector is proposed to further enhance noise and spur reduction performance. It is also shown that the FIR filtering not only suppresses out-of-band quantization noise but also improves in-band noise by mitigating the nonlinearity effect of the charge pump. Behavior simulation results show that the proposed semidigital ΔΣ PLL improves the in-band noise and reference spur performance by 20dB compared with the conventional ΔΣ PLL.
机译：本文在采用有限脉冲响应（FIR）滤波技术进行量化降噪的半数字ΔΣ锁相环（PLL）的设计中，介绍了一种采用混合相位检测的降噪方法。解决了静态相位偏移问题，并提出了使用混合相位检测器来进一步增强噪声和降低杂散的性能。还表明，FIR滤波不仅可以抑制带外量化噪声，而且还可以通过减轻电荷泵的非线性效应来改善带内噪声。行为仿真结果表明，与传统的ΔΣPLL相比，所提出的半数字ΔΣPLL将带内噪声和参考杂散性能提高了20dB。

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