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首页> 外文会议>IEEE Custom Integrated Circuits Conference >A 2.4-GHz ΔΣ Fractional-N Synthesizer with Space-Time Averaging for Noise Reduction
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A 2.4-GHz ΔΣ Fractional-N Synthesizer with Space-Time Averaging for Noise Reduction

机译：具有时空平均功能的2.4GHzΔΣ小数N分频合成器

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摘要

This paper presents a highly digital technique that can significantly reduce the quantization noise of fractional-N phase-locked loops (PLLs) at all frequencies. This is achieved by using an array of dividers to realize spatial averaging. A fractional ΔΣ modulator (DSM) and a data-weighted averaging (DWA) module are used to generate the vector division ratio for the divider array. Based on this technique, a 2.4-GHz fractional-N frequency synthesizer is implemented in 40 nm CMOS process, in which spatial averaging is achieved with only one divider and phase selection to lower the power. Measurement results show that the phase noise at 1 MHz and 10 MHz frequency offsets are improved by 8 dB and 20 dB, respectively, compared to the conventional architecture. The output root-mean-square (rms) jitter is reduced from 10.4 ps to 3.1 ps, same as that at integer mode. The proposed synthesizer consumes only 4.9 mW in total, leading to a FoM of -223.3 dB.
机译：本文提出了一种高度数字化的技术，该技术可以在所有频率上显着降低分数N锁相环（PLL）的量化噪声。这是通过使用一个分频器阵列实现空间平均来实现的。分数ΔΣ调制器（DSM）和数据加权平均（DWA）模块用于生成除法器阵列的矢量除法比。基于此技术，在40 nm CMOS工艺中实现了2.4 GHz分数N频率合成器，其中仅使用一个分频器和相位选择即可实现空间平均，以降低功耗。测量结果表明，与传统架构相比，在1 MHz和10 MHz频偏处的相位噪声分别提高了8 dB和20 dB。输出的均方根（rms）抖动从10.4 ps降低到3.1 ps，与整数模式相同。拟议的合成器总共仅消耗4.9 mW，导致-223.3 dB的FoM。

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