A 7b 2.6mW 900MS/s Nonbinary 2-then-3b/cycle SAR ADC with Background Offset Calibration

机译：具有背景失调校准的7b 2.6mW 900MS / s非二进制2-then-3b / cycle SAR ADC

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This paper presents a high speed nonbinary 2-then3b/cycle SAR ADC with background offset calibration. By exploiting comparators with two input paths, multiplication and subtraction can be performed in comparators instead of extra DAC array, resulting in reduced area and power overhead. Pseudo asynchronous clock as well as boundary detection mapping scheme are utilized to suppress metastability. Furthermore, a self background offset calibration, without external inputs or DAC configuration, is implemented on chip to ensure PVT robustness. A 7-bit prototype SAR ADC fabricated in 40nm LP CMOS achieves 39.7dB SNDR at 900MS/s sampling rate and consumes 2.6mW, resulting in a Nyquist FoM of 36.6fJ/conv-step.

机译：本文提出了一种具有背景失调校准的高速非二进制2-then3b / cycle SAR ADC。通过利用具有两个输入路径的比较器，可以在比较器中执行乘法和减法运算，而不是在额外的DAC阵列中进行运算，从而减小了面积并降低了功耗。利用伪异步时钟以及边界检测映射方案来抑制亚稳定性。此外，在芯片上实现了无需外部输入或DAC配置的自背景偏移校准，以确保PVT的鲁棒性。一个采用40nm LP CMOS制成的7位原型SAR ADC，在900MS / s采样率下可达到39.7dB SNDR，消耗2.6mW的功率，从而使奈奎斯特FoM为36.6fJ / conv-step。

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《IEEE Custom Integrated Circuits Conference》|2019年|1-4|共4页
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Dengquan Li; Jiaxin Liu; Haoyu Zhuang; Zhangming Zhu; Yintang Yang; Nan Sun;
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Calibration; Redundancy; Transistors; Clocks; Gain; Thermometers; Capacitors;

机译：校准;冗余;晶体管;时钟;增益;温度计;电容器;

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专利

1. A Decision-Error-Tolerant 45 nm CMOS 7b 1 GS/s Nonbinary 2b/Cycle SAR ADC [J] . Hong H.-K., Kim W., Kang H.-W., Solid-State Circuits, IEEE Journal of . 2015,第2期

机译：决策误差容限45 nm CMOS 7b 1 GS / s非二进制2b /周期SAR ADC
2. A 7-bit 900-MS/s 2-Then-3-bit/cycle SAR ADC With Background Offset Calibration [J] . Dengquan Li, Zhangming Zhu, Jiaxin Liu, Solid-State Circuits, IEEE Journal of . 2020,第11期

机译：带有背景偏移校准的7位900-MS / S 2-3位/周期SAR ADC
3. A Redundancy-Based Background Calibration for Comparator Offset/Threshold and DAC Gain in a Ping-Pong SAR ADC [J] . Bunsen Keigo, Martens Ewout, Dermit Davide, IEEE transactions on circuits and systems. II, Express briefs . 2021,第2期

机译：用于比较器偏移/阈值和DAC增益的冗余基于背景校准在乒乓球ADC中
4. A 7b 2.6mW 900MS/s Nonbinary 2-then-3b/cycle SAR ADC with Background Offset Calibration [C] . Dengquan Li, Jiaxin Liu, Haoyu Zhuang, IEEE Custom Integrated Circuits Conference . 2019

机译：带有背景偏移校准的7B 2.6MW 900ms / s非平二2-Thin-3B /循环SAR ADC
5. Background digital calibration of SAR ADC with fast FPGA emulation. [D] . Wang, Guanhua. 2013

机译：具有快速FPGA仿真功能的SAR ADC的后台数字校准。
6. Time-Interleaved SAR ADC with Background Timing-Skew Calibration for UWB Wireless Communication in IoT Systems [O] . Kiho Seong, Dong-Kyu Jung, Dong-Hyun Yoon, 2020

机译：物联网系统中用于UWB无线通信的具有时间时序校正的时间交错SAR ADC
7. A Time-Interleaved 2b/Cycle SAR ADC with Background Offset Calibration [O] . Shahaboddin Ghajari, Mohammad Sharifkhani 2018

机译：具有背景偏移校准的时间交织2B /循环SAR ADC

A 7b 2.6mW 900MS/s Nonbinary 2-then-3b/cycle SAR ADC with Background Offset Calibration

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