A 2-way 7.3-bit 10 GS/s Time-based Folding ADC with Passive Pulse-Shrinking Cells

机译：具有无源脉冲收缩单元的2路7.3位10 GS / s基于时间的折叠ADC

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This paper presents a two-way time-based folding ADC that uses a passive pulse shrinking (PPS) technique to quantize fine time resolution with a purely passive R-C network. A time folding, and subtraction circuit is introduced to further increase the dynamic range of the ADC without adding more PPS cells. The prototype is implemented in 65nm CMOS and achieves 32.5dB SNDR at 5.001GHz input frequency with the sampling rate of 10GS/s while consuming 29.7mW and occupying an area of 0.015mm², yielding an FOM of 86fJ/c-step.

机译：本文提出了一种基于双向基于时间的折叠式ADC，它使用无源脉冲收缩（PPS）技术通过纯无源R-C网络来量化精细的时间分辨率。引入了时间折叠和减法电路，以进一步增加ADC的动态范围，而无需增加更多的PPS单元。该原型在65nm CMOS中实现，并在5.001GHz输入频率下达到32.5dB SNDR，采样率为10GS / s，而功耗为29.7mW，面积为0.015mm。 ^{2
，FOM为86fJ / c-step。}

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《IEEE Custom Integrated Circuits Conference》|2019年|1-4|共4页
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Mohsen Hassanpourghadi; Mike Shuo-Wei Chen;
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Clocks; Calibration; Delays; Pulse width modulation; Prototypes; Image edge detection; Detectors;

机译：时钟;校准;延迟;脉冲宽度调制;原型;图像边缘检测;检测器;

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1. A 4-GS/s 11.3-mW 7-bit Time-Based ADC With Folding Voltage-to-Time Converter and Pipelined TDC in 65-nm CMOS [J] . Yi Il-Min, Miura Naoki, Nosaka Hideyuki IEEE Journal of Solid-State Circuits . 2021,第2期

机译：基于4GS / s 11.3-MW 7位时间的ADC，具有折叠电压与时转换器和65-NM CMOS的流水线TDC
2. A 10-GS/s 8-bit 4-way interleaved folding ADC in 0.18 mu m SiGe-BiCMOS [J] . Liu Huasen, Wu Danyu, Zhou Lei, Annals of the American Thoracic Society . 2019,第3期

机译：在0.18 mu m sige-bicmos中的10gs / s 8位4路交错折叠adc
3. A 10-GS/s 8-bit 4-way interleaved folding ADC in 0.18 μm SiGe-BiCMOS [J] . Huasen Liu, Danyu Wu, Lei Zhou, IEICE Electronics Express . 2019,第3期

机译：在0.18μmsige-bicmos中，10gs / s 8位4路交织折叠adc
4. A 2-way 7.3-bit 10 GS/s Time-based Folding ADC with Passive Pulse-Shrinking Cells [C] . Mohsen Hassanpourghadi, Mike Shuo-Wei Chen IEEE Custom Integrated Circuits Conference . 2019

机译：具有无源脉冲缩小电池的双向7.3位10GS / S时间折叠ADC
5. A single-channel 10b 1GS/s ADC with 2-cycle latency using pipelined cascaded folding architecture [D] . Razzaghi, Alireza 2008

机译：使用流水线级联折叠架构的单通道10b 1GS / s ADC具有2个周期的延迟
6. Passive transfer of flt-3L-derived dendritic cells delays diabetes development in NOD mice and associates with early production of interleukin (IL)-4 and IL-10 in the spleen of recipient mice [O] . J MORIN, B FAIDEAU, M-C GAGNERAULT, 2003

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7. A 1 GS/s 12-bit pipelined folding ADC with a novel encoding algorithm [O] . Huasen Liu, Danyu Wu, Lei Zhou, 2019

机译：具有新颖的编码算法的1 GS / S 12位流水线折叠ADC

A 2-way 7.3-bit 10 GS/s Time-based Folding ADC with Passive Pulse-Shrinking Cells

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