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A 2048-Neuron Spiking Neural Network Accelerator With Neuro-Inspired Pruning And Asynchronous Network On Chip In 40nm CMOS

机译：具有神经启发性修剪功能和40nm CMOS片上异步网络的2048-Neuron Spiking神经网络加速器

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A 40nm, 2.56mm², 2048-neuron globally asynchronous locally synchronous (GALS) spiking neural network (SNN) chip is presented. For scalability, we allow neurons to specialize to excitatory or inhibitory, and apply distance-based pruning to cut communication and memory. An asynchronous router limits the latency to 1.32ns per hop. The reduced traffic and lower latency allow the input channel to be parallelized to achieve 7.85GSOP/s at 0.7V, consuming 5.9pJ/SOP.

机译：40nm，2.56mm ^{2
提出了2048神经元全局异步局部同步（GALS）尖峰神经网络（SNN）芯片。为了实现可扩展性，我们允许神经元专门研究兴奋性或抑制性，并应用基于距离的修剪来减少交流和记忆。异步路由器将延迟限制为每跳1.32ns。减少的通信量和较低的延迟使输入通道可以并行化，以在0.7V时达到7.85GSOP / s，消耗5.9pJ / SOP。}

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《IEEE Custom Integrated Circuits Conference》|2019年|1-4|共4页
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Sung-Gun Cho; Edith Beigné; Zhengya Zhang;
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Neurons; Clocks; Synapses; Synchronization; System recovery; Routing; Image coding;

机译：神经元;时钟;突触;同步;系统恢复;路由;图像编码;

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专利

1. A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS [J] . Chen Gregory K., Kumar Raghavan, Sumbul H. Ekin, IEEE Journal of Solid-State Circuits . 2019,第4期

机译：4096-Neuron 1M-Synapse 3.8pJ / SOP尖峰神经网络，具有片上STDP学习功能和10nm FinFET CMOS的稀疏权重
2. A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS [J] . Chen Gregory K., Kumar Raghavan, Sumbul H. Ekin, IEEE Journal of Solid-State Circuits . 2019,第4期

机译：一个4096-neuron 1m-synapse 3.8-pj / sop尖刺神经网络，带有片上的stdp学习和稀疏的10-nm finfet cmos
3. STICKER: An Energy-Efficient Multi-Sparsity Compatible Accelerator for Convolutional Neural Networks in 65-nm CMOS [J] . Yuan Zhe, Liu Yongpan, Yue Jinshan, IEEE Journal of Solid-State Circuits . 2020,第2期

机译：贴纸：65-NM CMOS的卷积神经网络的节能多稀稀兼容性加速器
4. A 2048-Neuron Spiking Neural Network Accelerator With Neuro-Inspired Pruning And Asynchronous Network On Chip In 40nm CMOS [C] . Sung-Gun Cho, Edith Beigné, Zhengya Zhang IEEE Custom Integrated Circuits Conference . 2019

机译：一个2048神经元尖峰神经网络加速器，在40nm CMOS中具有神经启发修剪和异步网络的神经网络加速器
5. Analog Spiking Neural Network Implementing Spike Timing-Dependent Plasticity on 65 nm CMOS [D] . Vincent, Luke. 2021

机译：模拟尖峰神经网络在65nm CMOS上实施尖刺时序依赖性可塑性
6. Neuromorphic Spiking Neural Networks and Their Memristor-CMOS Hardware Implementations [O] . Luis A. Camuñas-Mesa, Bernabé Linares-Barranco, Teresa Serrano-Gotarredona 2019

机译：神经形态尖峰神经网络及其忆阻器CMOS硬件实现
7. Hybrid Spintronic-CMOS Spiking Neural Network with On-Chip Learning: Devices, Circuits, and Systems [O] . Abhronil Sengupta, Aparajita Banerjee, Kaushik Roy 2016

机译：杂交闪光CMOS尖刺神经网络，具有片上学习：设备，电路和系统
8. CMOS-based Stochastically Spiking Neural Network for Optimization under Uncertainties. [R] . Trivedi, A. R., Mukhopadhyay, S. 2017

机译：基于CmOs的随机尖峰神经网络在不确定条件下优化。

A 2048-Neuron Spiking Neural Network Accelerator With Neuro-Inspired Pruning And Asynchronous Network On Chip In 40nm CMOS

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