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首页> 外文会议>IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics >Matrix based Error Detection and Correction using Minimal Parity Bits for Memories
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Matrix based Error Detection and Correction using Minimal Parity Bits for Memories

机译：基于矩阵的错误检测和校正，使用最小奇偶校验位进行记忆

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摘要

Advancement in Complementary Metal Oxide Semiconductor (CMOS) technology causes Multiple Cell Upsets (MCUs). Due to the radiation particles, MCUs had been a challenging issue for data storage in memory for different applications. One of the techniques which is more often used to protect memories is Error Correction Code, because of their low complexity encoding and decoding. Generally, MCUs affect adjacent bits stored in the memory. Therefore, the technique which would detect and correct the adjacent bits as many as possible would be a productive technique. The only drawback with Matrix based code is the required number of parity bits which is used to support error correction in memories is very high. To resolve the drawback, we worked to minimise the number of parity bits in this paper. The proposed technique has equal error correction capability with smaller count of parity bits as compared to other existing techniques. Total parity bits has been reduced by 30% and area, power and delay time has been reduced by 1.12%, 33.59%, 55.46% respectively. These parameters make the proposed technique an efficient and productive one for protecting memories. This technique can be used in applications which have very strict constraints Of parity bits and speed.
机译：互补金属氧化物半导体（CMOS）技术的进步导致多个细胞扰（MCU）。由于辐射粒子，MCU对于不同应用程序中的存储器中的数据存储是一个具有挑战性的问题。由于它们的复杂性编码和解码，更常用于保护存储器的技术之一是纠错码。通常，MCU会影响存储在存储器中的相邻位。因此，可以检测和校正尽可能多的相邻位的技术将是生产性技术。基于矩阵的代码的唯一缺点是用于在存储器中支持纠错的奇偶校验比特数量非常高。要解决缺点，我们工作以最小化本文的奇偶校验位数。所提出的技术具有相同的误差校正能力，与其他现有技术相比具有较小的奇偶校验位计数。总奇偶校验位减少了30％，电力和延迟时间分别降低了1.12％，33.59％，分别为55.46％。这些参数使得提出的技术是一种用于保护存储器的有效和生产力的技术。该技术可用于具有非常严格的奇偶阶段和速度限制的应用。

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