• 主题
高级搜索  >
历史搜索 清空历史
首页> 外文会议>International Conference on Electronics, Information, and Communication >Hardware Implementation of ECIES Protocol on Security SoC
【24h】

Hardware Implementation of ECIES Protocol on Security SoC

机译：ECIES协议在安全SoC上的硬件实现

获取原文
页面导航
  • 摘要
  • 著录项
  • 相似文献
  • 相关主题

摘要

This paper describes a hardware implementation of ECIES (Elliptic Curve Integrated Encryption Scheme) protocol using a security SoC (System on Chip). The security SoC based on Cortex-M0 microcontroller integrates four cryptographic cores including ECC (Elliptic Curve Cryptography) core, SHA3 (Secure Hash Algorithm 3) core, UAAP (United ARIA and AES Processor) core, and TRNG (True Random Number Generator) core, which are connected to AHB-Lite. The ECC core is used for public key generation and key agreement function, and the SHA3 core is used for key derivation function. In addition, the block cipher AES is used for encryption/decryption and CBC-MAC. The security SoC was implemented in FPGA device, and the ECIES protocol was validated by hardware-software co-verification.
机译：本文介绍了使用安全SoC（片上系统）的ECIES（椭圆曲线集成加密方案）协议的硬件实现。基于Cortex-M0微控制器的安全SoC集成了四个加密核心，包括ECC（椭圆曲线密码学）核心，SHA3（安全哈希算法3）核心，UAAP（联合ARIA和AES处理器）核心和TRNG（真实随机数发生器）核心，它们连接到AHB-Lite。 ECC内核用于公钥生成和密钥协商功能，而SHA3内核用于密钥派生功能。另外，分组密码AES用于加密/解密和CBC-MAC。该安全性SoC在FPGA器件中实现，并且ECIES协议已通过软硬件协同验证进行了验证。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱：kefu@zhangqiaokeyan.com

京公网安备：11010802029741号 ICP备案号：京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有

  • 客服微信

  • 服务号