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首页> 外文会议>International Reliability Physics Symposium >Study of the Walk-Out Effect of Junction Breakdown Instability of the High-Voltage Depletion-Mode N-Channel MOSFET for NAND Flash Peripheral Device and an Efficient Layout Solution
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Study of the Walk-Out Effect of Junction Breakdown Instability of the High-Voltage Depletion-Mode N-Channel MOSFET for NAND Flash Peripheral Device and an Efficient Layout Solution

机译：用于NAND闪存外围设备的高压耗尽型N沟道MOSFET结击穿不稳定性的走出效应及其高效布局研究。

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摘要

In this paper, we report the junction breakdown instability of a depletion-mode high-voltage NMOSFET (DN) used in the NAND Flash peripheral circuit. Such DN device needs to sustain the highest voltage (>30V) during NAND Flash programming [1]-[2]. We observed instability of the junction breakdown in the product chip. Electrical measurement shows that the first measured breakdown voltage (BVDSS) from virgin state is usually lower than that after stress, which is called the "walk-out" effect [3]-[4]. The walk-out effect can be recovered by a high-temperature baking, indicating it’s not a permanent damage. TCAD simulation suggests that gate edge hole trapping by the band-to-band tunneling injection is the root cause of such walk-out effect [5]-[6]. The conventional layout structure of the DN has a large overlap of the buried-channel N-type doping with the light-doped drain (LDD), leading to the worse walk-out effect than normal HV NMOS. To suppress this effect, we propose an optimal layout design method of DN to avoid the overlap of N-type buried-channel doping with the LDD. Experimental results show very good improvements of BVDSS with acceptable transistor performances.
机译：在本文中，我们报告了用于NAND闪存外围电路的耗尽型高压NMOSFET（DN）的结击穿不稳定性。此类DN设备在NAND闪存编程[1]-[2]期间需要维持最高电压（> 30V）。我们观察到产品芯片中结击穿的不稳定性。电气测量表明，首次测得的击穿电压（BV DSS ）从原始状态开始通常比受到压力后的状态要低，这被称为“走动”效应[3]-[4]。走出效应可以通过高温烘烤来恢复，这表明这不是永久性损坏。 TCAD模拟表明，通过带间隧道注入注入栅边缘空穴是这种走动效应的根本原因[5]-[6]。 DN的常规布局结构具有掩埋沟道N型掺杂与轻掺杂漏极（LDD）的较大重叠，从而导致比普通HV NMOS产生更差的走出效果。为了抑制这种影响，我们提出了一种最佳的DN布局设计方法，以避免N型掩埋沟道掺杂与LDD重叠。实验结果表明BV有很好的改善 DSS 具有可接受的晶体管性能。

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