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首页> 外文会议>IEEE Symposium on VLSI Circuits >Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS
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Embedded PLL Phase Noise Measurement Based on a PFD/CP MASH 1-1-1 ΔΣ Time-to-Digital Converter in 7nm CMOS

机译：基于7nm CMOS的PFD / CP MASH 1-1-1ΔΣ时间数字转换器的嵌入式PLL相位噪声测量

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摘要

We propose an embedded PLL phase noise measurement macro for cost-effective SoC test based on a phase-frequency detector/charge pump (PFD/CP) MASH 1-1-1 ΔΣ time-to-digital converter (TDC). The decimated TDC output stream is post-processed to extract the phase jitter and noise spectrum. Measuring low jitter requires a short and precise reference delay which we generate with a charge-based pseudo-DLL that locks to the reference delay itself. Using a 14GHz LC-PLL built in 7nm CMOS as a demonstration vehicle, this macro measures 2.80ps rms jitter which closely matches 2.89ps measured by a phase noise analyzer. The built-in self-test (BIST) macro consumes 12.2mW on a 1.2V supply, occupying only 0.066mm2 which is only one-third of the PLL area.
机译：我们提出了一种基于相位频率检测器/电荷泵（PFD / CP）MASH 1-1-1ΔΣ时对数字转换器（TDC）的成本效益SOC测试的嵌入式PLL相位噪声测量宏。被抽取的TDC输出流被处理后处理以提取相位抖动和噪声频谱。测量低抖动需要短且精确的参考延迟，我们使用基于电荷的伪DLL生成，该伪DLL锁定到参考延迟本身。使用以7nm CMOS内置的14GHz LC-PLL为演示车辆，这种宏观测量2.80ps刚刚与相位噪声分析仪测量的2.89ps紧密匹配。内置自检（BIST）宏在1.2V电源上消耗12.2mW，占用0.066毫米 2 这仅是PLL区域的三分之一。

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