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Towards Optimal Topology Aware Quantum Circuit Synthesis

机译：走向最佳拓扑感知量子电路综合

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We present an algorithm for compiling arbitrary unitaries into a sequence of gates native to a quantum processor. As CNOT gates are error-prone for the foreseeable Noisy-Intermediate-Scale Quantum devices era, our A* inspired algorithm minimizes their count while accounting for connectivity. We discuss the formulation of synthesis as a search problem as well as an algorithm to find solutions. For a workload of circuits with complexity appropriate for the NISQ era, we produce solutions well within the best upper bounds published in literature and match or exceed hand tuned implementations, as well as other existing synthesis alternatives. In particular, when comparing against state-of-the-art available synthesis packages we show 2.4× average (up to 5.3×) reduction in CNOT count. We also show how to re-target the algorithm for a different chip topology and native gate set while obtaining similar quality results. We believe that tools like ours can facilitate algorithmic exploration and guide gate set discovery for quantum processor designers, as well as being useful for optimization in the quantum compilation tool-chain.
机译：我们提出了一种将任意unit编译为量子处理器固有的门序列的算法。由于CNOT门在可预见的噪声中级量子设备时代很容易出错，因此我们的A *启发算法在考虑连接性的同时将其数量降至最低。我们讨论了将合成公式化为搜索问题以及寻找解决方案的算法。对于复杂的电路工作量（适合NISQ时代），我们提供的解决方案要在文献中公布的最佳上限之内，并达到或超过手动调整的实现，以及其他现有的综合替代方案。特别是，与最先进的可用合成程序包进行比较时，我们发现CNOT计数平均减少了2.4倍（最多5.3倍）。我们还展示了如何针对不同的芯片拓扑和本机门集重新定位算法，同时获得相似的质量结果。我们相信像我们这样的工具可以促进量子处理器设计人员的算法探索和指导门集发现，并且对于量子编译工具链中的优化很有用。

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