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首页> 外文会议>IEEE Aerospace Conference >Designing Printed Circuit Boards to Drastically Reduce the Occurrence of Tombstoned Components
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Designing Printed Circuit Boards to Drastically Reduce the Occurrence of Tombstoned Components

机译：设计印刷电路板以大幅度减少墓碑形零件的出现

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Electronic components continue to shrink as electronic printed circuit boards become denser. Smaller discrete passive devices such as surface mount capacitors and resistors are increasing in use and approaching sizes that require magnification to recognize. Unfortunately, during the Surface Mount Technology (SMT) assembly process these smaller devices are the primary source of defects during soldering. One of the leading defects during SMT is “Tombstoning,” a condition where a capacitor or resistor only solders on one end due to vertical rotation of the component creating an open circuit. Rework is costly and potentially induces additional factors that can decrease overall reliability because rework requires heating the defect location multiple times with a soldering iron; once to remove and once to replace for each pad. This defect can be drastically reduced by using the correct printed circuit board design parameters when laying out the board pad geometries. Printed Circuit Board pad size and geometry play a significant role in reducing and eliminating “tombstoning.” This paper presents the results from a comprehensive Designed Experiment illustrating the effects of different pad designs and their effect on the amount of defects. The results show that smaller pad geometries are a major factor in the reduction of “tombstoning.” This combined with the elimination of solder mask between the pads yield significant reduction in SMT soldering defects. This paper will delineate the major factors involved and how a comprehensive Design of Experiment (DOE) was planned and performed to drastically reduce this type of defect.
机译：随着电子印刷电路板的密度增大，电子组件继续缩小。诸如表面贴装电容器和电阻器之类的较小的分立无源器件的使用正在增加，并且其尺寸接近需要放大才能识别的大小。不幸的是，在表面贴装技术（SMT）组装过程中，这些较小的设备是焊接过程中缺陷的主要来源。 SMT期间的主要缺陷之一是“ Tombstoning”，这种情况是由于组件的垂直旋转导致电容器或电阻器仅在一端焊接，从而形成开路。返工成本很高，并且可能会导致其他因素，从而降低整体可靠性，因为返工需要使用烙铁多次加热缺陷位置。一次移除一次，一次更换一次。通过在布局电路板焊盘几何形状时使用正确的印刷电路板设计参数，可以大大减少此缺陷。印刷电路板的焊盘尺寸和几何形状在减少和消除“墓碑”方面起着重要作用。本文介绍了来自全面设计实验的结果，该实验说明了不同焊盘设计的影响及其对缺陷数量的影响。结果表明，较小的焊盘几何形状是减少“墓碑”的主要因素。这与消除焊盘之间的阻焊层相结合，可显着减少SMT焊接缺陷。本文将描述涉及的主要因素，以及如何计划和执行全面的实验设计（DOE）以大幅度减少此类缺陷。

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