One of the obstacles to using RISC processors in a hard real-timeenvironment is the unpredictability of caches. This unpredictabilitystems from basing them on a design that tries to optimize the averagecase execution time. We propose a dual mode instruction prefetch schemeas an alternative to instruction caching schemes. In the proposedscheme, a thread is associated with each instruction block. The threadindicates the instruction block that is to be prefetched once the blockcontaining it is accessed by the processor. The proposed scheme operatesin two different modes: real-time and non real-time modes. In thereal-time mode, the prefetching of instruction blocks is made in thedirection that improves the worst case execution time. For this purpose,the thread is generated by the compiler through an analysis of the worstcase execution path. In the non real-time mode, the thread isdynamically updated so that it indicates the instruction block that ismost likely to be accessed next is the block that was previouslyaccessed after the present block. Therefore, the thread is made to pointto such a block in the non real-time mode. The above tailoring of threadinformation is on a task basis and, therefore, each task in the systemcan choose its own mode depending on its needs. Typically real-timetasks choose the real-time mode for an improved worst case executiontime whereas non time critical tasks choose the non real-time mode foran improved average case execution time. This paper shows, throughanalysis using a timing tool, that the proposed scheme significantly (upto 45%) improves the predicted worst case execution time in thereal-time mode as compared with no prefetching scheme
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