首页> 外文会议>2010 11th International Workshop on Symbolic and Numerical Methods, Modeling and Applications to Circuit Design >Low voltage low power neuron circuit design based on subthreshold FGMOS transistors and XOR implementation
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Low voltage low power neuron circuit design based on subthreshold FGMOS transistors and XOR implementation

机译:基于亚阈值FGMOS晶体管的低压低功耗神经元电路设计和XOR实现

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In this work, design of low-voltage low-power analog artificial neural network (ANN) circuit blocks by using subthreshold floating-gate MOS (FGMOS) transistors and a neuron circuit is implemented. The circuit blocks, four-quadrant analog current multiplier and FGMOS based differential pair, have been designed and simulated in CADENCE environment with TSMC 0.35µm process parameters. Using the proposed neuron circuits a neural network was realized. XOR problem was applied to test accuracy of the network and the results were concluded.
机译:在这项工作中,实施了通过使用亚阈值浮栅MOS(FGMOS)晶体管和神经元电路来设计低压低功率模拟人工神经网络(ANN)电路块的设计。电路块,四象限模拟电流倍增器和基于FGMOS的差分对,在具有TSMC0.35μm工艺参数的Cadence环境中设计和模拟。使用所提出的神经元电路实现了神经网络。 XOR问题应用于测试网络的准确性,结果得出结论。

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