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首页> 外文会议>15th AIAA International Communications Satellite Systems Conference February 27-March 3, 1994-San Diego, CA >Fault Tolerant Onboard Packet Switch Architecture for Communication Satellites: Shared memory Per Beam Approach
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Fault Tolerant Onboard Packet Switch Architecture for Communication Satellites: Shared memory Per Beam Approach

机译：通信卫星的容错机载分组交换架构：每波束共享内存方法

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摘要

The NASA Lewis Research Center is developing a multichannel communication signal processing satellite (MCSPS) system which will provide low data rate, direct to user, commercial communications services. The focus of current space segment developments is a flexible, high-throughput, fault tolerant onboard information switching processor. This information switching processor (ISP) is a destination-directed packet switch which performs both space and time switching to route user infromation among numerous user ground terminals. Through both industry study contracts and in-house investigations, several packet switching architectures were examined. A contention-free approach, the shared memory per beam architecture, was selected for implementation. This paper describes the shared memory per beam architecture, fault tolerance insertion, implementation, and demonstration plans.
机译：美国宇航局刘易斯研究中心正在开发一种多通道通信信号处理卫星（MCSPS）系统，该系统将提供低数据速率，直接向用户提供商业通信服务。当前空间分段开发的重点是灵活的，高吞吐量，容错的机载信息交换处理器。该信息交换处理器（ISP）是一个目标定向的分组交换机，它执行空间和时间交换，以在众多用户地面终端之间路由用户信息。通过行业研究合同和内部调查，研究了几种数据包交换体系结构。选择了一种无竞争的方法，即每个波束架构的共享内存来实现。本文介绍了每个波束架构的共享内存，容错插入，实现和演示计划。

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