Sample Mounting Methods for Precision Delayering of 130 nm Integrated Circuit Devices

机译：用于130nm集成电路器件的精确延迟的样本安装方法

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This paper reviews different methods for mounting and integrated circuit (IC) for delayering. In this work, several 130nm technology devices are observed during the delayering process as a means of evaluating the advantages and disadvantages of various mounting techniques. Suitability for chemical mechanical polishing, wet etching, and dry etching is considered.

机译：本文介绍了用于延迟安装和集成电路（IC）的不同方法。在这项工作中，在延迟过程中观察到几个130nm技术设备，作为评估各种安装技术的优点和缺点的手段。考虑了化学机械抛光，湿法蚀刻和干蚀刻的适用性。

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《IEEE International Conference on Physical Assurance and Inspection on Electronics》|2020年|1-5|共5页
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Jonathan Scholl; Yash Patel; Joshua Baur; Adam Kimura; Adam Waite; John Kelley; Glen David Via;
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Integrated circuits; Wet etching; Metals; Standardization; Tools; Surface treatment; Paints;

机译：集成电路;湿蚀刻;金属;标准化;工具;表面处理;油漆;

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专利

1. An Efficient Le-fdtd Method For The Analysis Of The Active Integrated Circuit And Antenna Mounted Non-linear Devices [J] . Kazuhiro FUJIMORI, Naoto KAWASHIMA, Minoru SANAGI, IEICE Transactions on Electronics . 2007,第9期

机译：一种有效的Le-fdtd方法，用于分析有源集成电路和天线安装的非线性器件
2. Switching Battery Charger Integrated Circuit for Mobile Devices in a 130-nm BCDMOS Process [J] . Min-Gyu Jeong, Sang-Hyun Kim, Changsik Yoo IEEE Transactions on Power Electronics . 2016,第11期

机译：130nm BCDMOS工艺中用于移动设备的开关电池充电器集成电路
3. Radiation Tolerance of Devices and Circuits in a 3D Technology Based on the Vertical Integration of Two 130-nm CMOS Layers [J] . Re V., Gaioni L., Manazza A., IEEE Transactions on Nuclear Science . 2013,第6aPart1期

机译：基于两个130nm CMOS层的垂直集成的3D技术中的设备和电路的辐射容限
4. A novel extended FDTD method for the analysis of the active integrated circuit and antenna mounted non- linear devices [C] . Kawashima Naoto, Fujimori Kazuhiro, Sanagi Minoru, Asia-Pacific Microwave Conference . 2006

机译：一种新型扩展FDTD方法，用于分析有源集成电路和天线安装的非线性装置
5. Methods of integrating SCREAM micromachined devices with integrated circuits. [D] . Shaw, Kevin Allan. 1998

机译：将SCREAM微加工设备与集成电路集成的方法。
6. Sub-10 nm colloidal lithography for circuit-integrated spin-photo-electronic devices [O] . Adrian Iovan, Marco Fischer, Roberto Lo Conte, 2012

机译：小于10 nm的胶体光刻技术用于电路集成自旋光电器件
7. Precision top-down delayering of microelectronics devices using broad-beam argon ion milling [O] . Pawel Nowakowski, Kristin Olexa, Mary Ray, 2016

机译：使用宽梁氩离子铣削进行微电子器件的精密自上而下延迟

Sample Mounting Methods for Precision Delayering of 130 nm Integrated Circuit Devices

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