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RT level testability analysis to reduce test application time

机译:RT水平可测试性分析降低测试应用时间

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Describes research activities, the goal of which is to develop a methodology that solves the problem of RT (register transfer) level (RTL) testability analysis in a complex way. On the basis of the RTL testability analysis, a substantial reduction in test application time can be achieved. A new model of RTL element classification for the purposes of RTL testability analysis is described. The prescription for an RTL circuit transformation to a labelled directed graph and its representation in a PROLOG environment are presented. The methodology for the RTL testability analysis and the principles of its implementation are described.
机译:描述了研究活动,其目标是开发一种方法,解决了一种以复杂的方式解决了RT(RTL)级(RTL)可测试性分析的问题。在RTL可测试性分析的基础上,可以实现测试施用时间的大幅降低。描述了一种新的RTL元素分类模型,用于RTL可测试性分析。提出了RTL电路变换对标记的指导图的处方及其在Prolog环境中的表示。描述了RTL可测试性分析的方法和其实现的原理。

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