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A DFT method for core-based systems-on-a-chip based on consecutive testability

机译：基于核心基于芯片的芯片的DFT方法，基于连续可测试性

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This paper introduces a new concept of testability of core-based systems-on-a-chip (SoCs) called consecutive testability and proposes a design for-testability (DFT) method for making a given SoC consecutively testable based on integer programming problem. For a consecutively testable SoC, testing can be performed as follows. Test patterns of a core are propagated to the core inputs from the SoC inputs consecutively at speed of system clock. Similarly the test responses are propagated to the SoC outputs from the core outputs consecutively at speed of system clock. The propagation of test patterns and responses is achieved by using the consecutive transparency properties of surrounding cores and interconnects between cores. All interconnects can be tested in a similar fashion. Therefore, the method can test not only logic faults such as stuck-at faults, but also timing faults such as delay faults that require consecutive application of test patterns at speed of system clock.
机译：本文介绍了一种新的基于芯片的芯片（SoC）的可测试性概念，称为连续可测试性，并提出了一种基于整数编程问题的给定SOC的设计（DFT）方法的设计。对于连续可测试的SOC，可以如下进行测试。核心的测试模式通过系统时钟的速度连续地传播到SOC输入的核心输入。类似地，测试响应在系统时钟的速度下连续地传播到来自核心输出的SOC输出。通过使用周围芯的连续透明性和核之间的互连来实现测试模式和响应的传播。所有互连都可以以类似的方式测试。因此，该方法不仅可以测试逻辑故障，例如卡在故障，还可以进行定时故障，例如需要连续应用测试模式以系统时钟的延迟故障。

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