This paper proposes alternative architectures to perform a circular correlation using the Fast Fourier Transform (FFT) by decomposing the initial circular correlation into several smaller circular correlations. The approach used is similar to the Fast Finite Impulse Response (FIR) Algorithms (FFAs). These architectures improve the performance in terms of reduced processing time or resource usage, and consequently lower the energy consumption. The results can be applied to any system that performs circular convolution or correlation. In this paper, the application is the acquisition of Global Navigation Satellite System (GNSS) signals with the FFT-based Parallel Code-phase Search (PCS), and more precisely on the GPS L1 C/A signal, when the target considered is a Field Programmable Gate Array (FPGA). In this context, it is for example shown that it is possible with one of the proposed architectures to reduce the logic usage by 11%, the memory usage by 41%, and the Digital Signal Processing (DSP) block usage by 32%, while keeping the same processing time. With another architecture, it is shown that the processing time can be halved by increasing the logic usage by only 35%, while reducing the memory usage and keeping the same DSP usage. Note that the proposed approach is not based on an approximation of the traditional method, but a modified implementation providing the same result. Thus, there is no loss of sensitivity.
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机译：本文提出了通过将初始循环相关性分解成几个较小的循环相关性来执行使用快速傅里叶变换（FFT）来执行圆周相关性的替代架构。使用的方法类似于快速有限脉冲响应（FIR）算法（FFA）。这些架构在减少处理时间或资源使用方面提高了性能，从而降低了能量消耗。结果可以应用于执行循环卷积或相关的任何系统。在本文中，应用是获取与基于FFT的并行代码相位搜索（PC）的全局导航卫星系统（GNSS）信号，并且在考虑目标的目标时更精确地达到GPS L1 C / A信号。现场可编程门阵列（FPGA）。在这种情况下，例如，可以使用其中一个提出的架构中的一个可以将逻辑用量降低11％，存储器使用量为41％，数字信号处理（DSP）块使用时间为32％保持相同的处理时间。利用另一种架构，示出了通过仅增加35％的逻辑使用量可以减少处理时间，同时降低存储器使用并保持相同的DSP使用。注意，所提出的方法不是基于传统方法的近似，而是提供相同的结果的修改实现。因此，没有敏感性损失。
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