首页> 外文会议>IEEE International Conference on Acoustics, Speech, and Signal Processing >AN IMPROVED PARALLEL ARCHUTECTURE FOR MPEG-4 MOTION ESTIMATION IN 3G MOBILE APPLICATIONS
【24h】

AN IMPROVED PARALLEL ARCHUTECTURE FOR MPEG-4 MOTION ESTIMATION IN 3G MOBILE APPLICATIONS

机译:用于3G移动应用中MPEG-4运动估计的改进的并行架构

获取原文

摘要

A high-parallel VLSI core architecture for MPEG-4 motion estimation is proposed in this paper. It possesses the characteristics of low memory bandwidth and low clock rate requirements, thus primarily aiming at 3G mobile applications. Based on a one-dimensional tree architecture, the architecture employs the dual-register/buffer technique to reduce the preload and alignment cycles. As an example, full-search block matching algorithm has been mapped onto this architecture using a 16-PE array that has the ability to calculate the motion vectors of QCIF video sequences in real time at 1 MHz clock rate and using 15.5 Mbytes/s memory bandwidth.
机译:本文提出了一种用于MPEG-4运动估计的高平行VLSI核心架构。它具有低存储器带宽和低时钟速率要求的特性,从而主要针对3G移动应用。基于一维树架构,该体系结构采用双寄存器/缓冲技术来减少预加载和对准周期。作为示例,使用16-PE阵列映射了全搜索块匹配算法,该算法映射到该架构上,该阵列能够在1 MHz时钟速率下实时计算QCIF视频序列的运动向量,并使用15.5 MBytes / S内存带宽。

著录项

相似文献

  • 外文文献
  • 中文文献
  • 专利
获取原文

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号