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Interface adaptor logic - a new model for interfacing peripherals in IP based designs

机译:接口适配器逻辑 - 基于IP设计中的外设接口外设的新模型

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The introduction of standard on-chip buses has eased integration and boosted the production of IP functional cores. However, once an IP is bus specific retargeting to a different bus is time-consuming and tedious, and this reduces the reusability of the bus-specific IP. As new bus standards are introduced and different interconnection methods are proposed, this problem increases. Many solutions have been proposed, however these solutions either limit the IP block performance or are restricted to a particular platform. A new concept is presented that can connect IP blocks to a wide variety of interface architectures with low overhead. This is achieved through the use a special interface adaptor logic layer.
机译:标准片上总线的引入已经缓解集成并提升了IP功能核的生产。但是,一旦IP是公共汽车特定的重新定位到不同的总线就耗时和繁琐,这降低了总线特定IP的可重用性。由于引入了新的总线标准,提出了不同的互连方法,因此此问题增加。已经提出了许多解决方案,但这些解决方案限制了IP块性能,或者限于特定平台。提出了一个新概念,可以将IP块连接到具有低开销的各种接口架构。这是通过使用特殊接口适配器逻辑层实现的。

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