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A low-power correlator for wakeup receivers with algorithm pruning through early termination

机译：具有早期终止算法修剪算法的唤醒接收器的低功耗相关器

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摘要

A low-complexity, low-power digital correlator for wakeup receivers is presented. With the proposed algorithm, unnecessary computational cycles are dynamically pruned from the correlation using an early threshold check. For the algorithm, we provide a rigorous mathematical analysis for the associated complexity/performance trade-offs. Furthermore, a low overhead hardware architecture with early-termination capability is developed and implemented in a 0.18μm CMOS technology. The post layout power analysis shows that the presented architecture can reduce power by up to 32% when compared to the conventional architecture with negligible degradation in detection probability and without degradation in false-alarm probability.
机译：提出了低复杂性，用于唤醒接收器的低功耗数字相关器。利用所提出的算法，使用早期阈值检查从相关性地动态地修剪不必要的计算周期。对于算法，我们为相关的复杂性/性能权衡提供了严格的数学分析。此外，在0.18μmCMOS技术中开发和实现具有早期终止能力的低开销硬件架构。后布局功率分析表明，与传统架构相比，所呈现的架构可以将功率降低至32％，在检测概率下可以忽略不计的造型，并且在错误警报概率中没有降解。

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