A design and implementation of high-speed 3DES algorithm system

机译：高速3DES算法系统的设计与实现

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This paper introduces the principle of 3DES encryption algorithm and the detailed description of the algorithm design and implementation on FPGA. For the improvement of the S-box, it uses a single S-box to replace the original eight S-boxes. This will not only greatly reduces the size of circuit but also reduces the power consumption of the entire circuit. In the design, pipelining technology is used to improve its running speed. All the modules are using Verilog HDL hardware description language to achieve, and at last it is downloaded to the FPGA chip.

机译：本文介绍了3DES加密算法的原理及FPGA对算法设计和实现的详细描述。为了改进S盒，它使用单个S盒来更换原始的八个S盒。这不仅会大大降低电路的大小，而且还可以降低整个电路的功耗。在设计中，流水线技术用于提高其运行速度。所有模块都使用Verilog HDL硬件描述语言来实现，最后它将其下载到FPGA芯片。

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来源
《International Conference on Future Information Technology and Management Engineering》|2009年||共4页
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作者
Yang Jun; Li Na; Ding Jun;
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原文格式 PDF
正文语种
中图分类 G202-53;
关键词
DES; 3DES; FPGA; Verilog HDL; Pipeline;

机译：des;3des;fpga;Verilog HDL;管道;

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A design and implementation of high-speed 3DES algorithm system

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