Design and implementation of truncated multipliers for precision improvement

机译：提高精度的截断乘法器的设计与实现

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Truncated multipliers offers significant improvements in area, delay, and power. The proposed'method finally reduces the number of full adders and half adders during the tree reduction. While using this proposed method experimentally, area can be saved. The output is in the form of LSB and MSB. Finally the LSB part is compressed by using operations such as deletion, reduction, truncation, rounding and final addition. In previous related papers, to reduce the truncation error by adding error compensation circuits. In this project truncation error is not more than 1 ulp (unit of least position). So there is no need of error compensation circuits, and the final output will be precised.

机译：截断乘法器在面积、延迟和功率方面提供了显著的改进。该方法最终减少了树约简过程中全加器和半加器的数量。在实验中使用这种方法，可以节省面积。输出的形式为LSB和MSB。最后，通过删除、减少、截断、舍入和最终添加等操作对LSB部分进行压缩。在以前的相关文献中，通过增加误差补偿电路来减小截断误差。在本项目中，截断误差不超过1 ulp（最小位置单位）。因此，不需要误差补偿电路，最终输出将被精确化。

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《ICCCI 2013;International Conference on Computer Communication and Informatics》|2013年||共5页
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作者
R. Devarani; C.S.Manikandababu;
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中图分类 TN919-532;
关键词
Computer arithmetic; faithful rounding; fixed- width multiplier; tree reduction; truncated multiplier.;

机译：计算机算法;忠实的四舍五入;固定宽度乘数;树木砍伐;截断乘数。;

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2. Design and Application of Faithfully Rounded and Truncated Multipliers With Combined Deletion, Reduction, Truncation, and Rounding [J] . Ko H.-J., Hsiao S.-F. Circuits and Systems II: Express Briefs, IEEE Transactions on . 2011,第5期

机译：组合删除，归约，截断和舍入的忠实舍入乘法器的设计和应用
3. The authors' replies to the discussion on ????????Improvements in the precision measurement of capacitance????????, ????????The design of an audio-frequency amplifier for high-precision voltage measurement????????, ????????The design and performance of high-precision audio-frequency current transformers???????? and ????????Techniques for the calibration of standard current transformers up to 20 kc/s???????? [J] . Rayner G.H., Ford L.H., Harkness S., Proceedings of the IEE - Part B: Electronic and Communication Engineering . 1961,第39期

机译：作者对?????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????????--------高精度电压测量高精度音频电流互感器的设计与性能以及用于标定高达20 kc / s的标准电流互感器的技术
4. Discussion on ????????Improvements in the precision measurement of capacitance????????, ????????The design of an audio-frequency amplifier for high-precision voltage measurement????????, ????????The design and performance of high-precision audio-frequency current transformers???????? and ????????Techniques for the calibration of standard current transformers up to 20 kc/s???????? before the Measurement and Control Section, 10th January, 1961 [J] . Proceedings of the IEE - Part B: Electronic and Communication Engineering . 1961,第39期

机译：关于电容精度测量的改进的讨论高精度测量电压的音频放大器的设计高精度音频电流互感器的设计与性能以及用于标定高达20 kc / s的标准电流互感器的技术1961年1月10日，在测量与控制科之前
5. Design and implementation of truncated multipliers for precision improvement [C] . Devarani R., Manikandababu C. S. 2013 International Conference on Computer Communication and Informatics. . 2013

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6. Design and implementation of a floating point multiplier using Altera's design environment and FPGAs [D] . Fox, Rafael. 1996

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9. Design and Performance Analysis of an Asynchronous Pipelined Multiplier with Comparison to Synchronous Implementation [R] . Shawhan, K. A. 2000

机译：异步流水线乘法器的设计与性能分析与同步实现的比较

Design and implementation of truncated multipliers for precision improvement

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