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Regular 2D NASIC-based architecture and design space exploration

机译:常规的2D基于纳斯的架构和设计空间探索

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As CMOS technology approaches its physical limits several emerging technologies are investigated to find the right replacement for the future computing systems. A number of different fabrics and architectures are currently under investigation. Unfortunately, at this time, no unified modeling exists to offer sound support for algorithmic design space exploration, with no compromise on device feasibility. This work presents a NASIC-compliant application-specific computing architecture template along with its performance models and optimization policies that support domain-space exploration. This architecture has up to 29X density advantage over CMOS, is completely compatible with the NASIC manufacturing pathway, and enables the creation of unique max-rate pipelined systems.
机译:随着CMOS技术接近其物理限制,调查了几种新兴技术,以找到未来计算系统的正确替代品。 目前正在调查许多不同的面料和架构。 遗憾的是,此时,不存在统一的建模,为算法设计空间探索提供声音支持,没有妥协的设备可行性。 此工作介绍了符合符合稳定的应用程序特定的计算体系结构模板,以及其性能模型和优化策略,支持域空间探索。 该架构通过CMOS高达29倍的密度优势,与鼻制造路径完全兼容,并能够创建独特的最大速率流水线系统。

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