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首页> 外文会议>International Symposium on Applied Reconfigurable Computing >Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs
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Hardware/Algorithm Co-optimization for Fully-Parallelized Compact Decision Tree Ensembles on FPGAs

机译：FPGA上全平行化的紧凑型决策树集合的硬件/算法共同优化

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Decision tree ensembles, such as random forests, are well-known classification and regression methods with high accuracy and robustness, especially for categorical data that combines multiple weak learners called decision trees. We propose an architecture/algorithm co-design method for implementing fully parallelized fast decision tree ensembles on FPGAs. The method first produces compact and almost equivalent representations of original input decision trees by threshold compaction. For each input feature, comparisons with similar thresholds are merged into fewer variations, so the number of comparisons is reduced. The decision tree with merged thresholds is perfectly extracted as hard-wired logic for the highest throughput. In this study, we developed a prototype hardware synthesis compiler that generates a Verilog hardware description language (HDL) description from a compressed representation. The experiment successfully demonstrates that the proposed method reduces the sizes of generated hardware without accuracy degradation.
机译：决策树集合（例如随机林）是具有高精度和稳健性的知名分类和回归方法，特别是对于组合多个弱学习者称为决策树的分类数据。我们提出了一种在FPGA上实现全部并行化的快速决策树集合的体系结构/算法共设计方法。该方法首先通过阈值压缩产生原始输入决策树的紧凑且几乎等同的表示。对于每个输入特征，具有类似阈值的比较被合并为更少的变化，因此减少了比较数量。具有合并阈值的决策树是完全提取为最高吞吐量的硬连线逻辑。在本研究中，我们开发了一个原型硬件综合编译器，可以从压缩表示中生成Verilog硬件描述语言（HDL）描述。实验成功地表明，所提出的方法减少了所生成的硬件的尺寸而不提供精度下降。

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