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Design technique for simultaneous reduction of leakage power and contention current for wide fan-in domino logic based 32:1 multiplexer circuit

机译：基于32：1多路复用器多米诺逻辑的同时降低泄漏功率和竞争电流的设计技术

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摘要

Domino circuits are becoming increasingly popular due to their speed and area advantages over their static counterparts. Every new generation of mobile processors employs domino circuits in critical paths to reduce delay. Multiplexers are one such combinational circuit finding extensive use in register files and execution units where data needs to be routed to one of the several operators. Power consumption, mainly due to contention and leakage currents poses problems of heat build up and performance degradation in domino circuits and this problem grows as the technology is scaled to subnanometer regimes. In this paper, a design technique has been proposed which reduces the contention and leakage currents simultaneously without much area overhead. The design has also been incorporated with a process variation sensor and simulations performed on the same to check for tolerance and the results have been found to conform to tolerance limits. The proposed technique uses only three extra transistors and minimizes contention current by about 74% and leakage by 38%, thus achieving a significant reduction in the average power consumption of the circuit.
机译：多米诺电路由于其速度和面积优于静态电路而变得越来越受欢迎。每个新一代的移动处理器都在关键路径中使用多米诺电路以减少延迟。多路复用器就是这样一种组合电路，可在寄存器文件和执行单元中广泛使用，其中数据需要路由到几个运算符之一。主要由于争用和泄漏电流引起的功耗造成了多米诺骨牌电路中的热量积聚和性能下降的问题，并且随着该技术扩展到亚纳米范围，该问题变得越来越严重。在本文中，提出了一种设计技术，该技术可在不增加面积开销的情况下同时减少竞争和泄漏电流。该设计还集成了过程变化传感器，并在该传感器上进行了仿真以检查公差，发现结果符合公差极限。所提出的技术仅使用三个额外的晶体管，将竞争电流最小化了约74％，将泄漏电流最小化了38％，从而显着降低了电路的平均功耗。

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