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Usefulness States in New P System Communication Architectures

机译:新P系统通信体系结构中的有用性状态

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摘要

Dealing with distributed implementations of P systems, the bottleneck communication problem has arisen. When the number of membranes grows up, the network get congested. In agreement with this, several published works have presented an analysis for different architectures, which implement P systems in a distributed cluster of processors, allocating several membranes to the same processor. The purpose of these architectures is to reach a compromise between the massively parallel character of the system and the needed evolution step time to transit from one configuration of the system to the next one, solving the bottleneck communication problem.rnThe work presented here carries out an analysis of semantics of the P systems, in several distributed architectures. It will be shown how to restructure P systems when dissolutions or inhibitions take place in membranes. Moreover, it will be also determined the extra information necessary at every communication step in order to allow all objects to arrive at their targets without penalizing the communication cost. This will be based on usefulness states, presented in a previous work, which allow each membrane of the system to know the set of membranes with which communication is possible at any time.
机译:在处理P系统的分布式实现时,出现了瓶颈通信问题。当膜的数量增加时,网络就会变得拥塞。与此相符的是,一些已发表的著作对不同的体系结构进行了分析,这些体系结构在处理器的分布式集群中实现P系统,并将多个膜分配给同一处理器。这些体系结构的目的是在系统的大规模并行特性与从系统的一种配置过渡到下一配置所需的演进步骤之间达成折衷,从而解决了瓶颈通信问题。在几种分布式体系结构中分析P系统的语义。将说明在膜中发生溶解或抑制时如何重建P系统。此外,还将确定在每个通信步骤中必需的额外信息,以允许所有对象到达其目标而不会损失通信成本。这将基于先前工作中提出的有用状态,这些状态使系统的每个膜都可以知道随时可以与之通信的膜组。

著录项

  • 来源
    《Membrane computing》|2008年|169-186|共18页
  • 会议地点 Edinburgh(GB);Edinburgh(GB)
  • 作者单位

    Dpto. de Lenguajes, Proyectos y Sistemas Informaticos Escuela Unversitaria de Informatica - Universidad Politecnica de Madrid Crta. de Valencia Km. 7 - 28031 Madrid - Spain;

    Dpto. de Lenguajes, Proyectos y Sistemas Informaticos Escuela Unversitaria de Informatica - Universidad Politecnica de Madrid Crta. de Valencia Km. 7 - 28031 Madrid - Spain;

    Dpto. de Lenguajes, Proyectos y Sistemas Informaticos Escuela Unversitaria de Informatica - Universidad Politecnica de Madrid Crta. de Valencia Km. 7 - 28031 Madrid - Spain;

  • 会议组织
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 混合集成电路;
  • 关键词

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