16-level Current-Mode Multiple-Valued Dynamic Memory with Increased Noise Margin

机译：具有更高噪声裕量的16级电流模式多值动态存储器

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摘要

Design and implementation of a novel 16-level multiple-valued memory is proposed. Each memory cell uses equivalent to one binary digit to detect the error due to leakage currents. Moreover, this feature increases the noise margin of the system by a factor of two. The refreshing circuitry is based on a series configuration of A/D and D/A converters for each data line. The error correction and storage scheme is based on a recently developed multiple-valued representation, called Continuous Valued Number System (CVNS). This memory cell can be used in hardware implementation of multiple-valued neural networks based on the CVNS.

机译：提出了一种新颖的16级多值存储器的设计与实现。每个存储单元使用相当于一个二进制数的位数来检测由于漏电流引起的错误。此外，此功能使系统的噪声容限增加了两倍。刷新电路基于每条数据线的A / D和D / A转换器的串联配置。纠错和存储方案基于最近开发的多值表示形式，称为连续值系统（CVNS）。该存储单元可用于基于CVNS的多值神经网络的硬件实现。

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《Multiple-Valued Logic, 2009. ISMVL '09》|2009年|48-53|共6页
会议地点 Naha(JP);Naha(JP)
作者
Khodabndehloo G.; Mirhassani M.; Ahmadi M.;
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Electr. Comput. Eng. Dept., Univ. of Windsor, Windsor, ON;

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DRAM chips; current-mode circuits; current-mode logic; multivalued logic; multivalued logic circuits; A/D converters; Continuous Valued Number System; D/A converters; binary digit; current-mode multiple-valued dynamic memory; leakage current; multiple-valued neural networks; multiple-valued representation; noise margin; refreshing circuitry; CVNS; error correction; memory; multiple-valued;

机译：DRAM芯片;电流模式电路;电流模式逻辑;多值逻辑;多值逻辑电路; A / D转换器;连续值系统; D / A转换器;二进制数字;电流模式多值动态存储器;漏电流;多值神经网络;多值表示;噪声余量;刷新电路; CVNS;纠错;内存;多值;

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专利

1. Power–Delay–Area–Noise Margin Tradeoffs in Positive-Feedback MOS Current-Mode Logic [J] . Alioto M., Pancioni L., Rocchi S., IEEE transactions on circuits and systems . I , Regular papers . 2007,第9期

机译：正反馈MOS电流模式逻辑中的功率-延迟-面积-噪声裕度折衷
2. New Architecture for Multiple-Valued Fine-Grain Reconfigurable VLSI Based on Current-Mode Logic [J] . Xu BAI, Michitaka KAMEYAMA 電子情報通信学会技術研究報告. 集積回路. Integrated Circuits and Devices . 2013,第236期

机译：基于电流模式逻辑的多值细粒度可重构VLSI的新架构
3. New Architecture for Multiple-Valued Fine-Grain Reconfigurable VLSI Based on Current-Mode Logic [J] . Xu BAI, Michitaka KAMEYAMA 電子情報通信学会技術研究報告. VLSI設計技術. VLSI Design Technologies . 2013,第235期

机译：基于电流模式逻辑的多值细粒度可重构VLSI的新架构
4. 16-level Current-Mode Multiple-Valued Dynamic Memory with increased Noise Margin [C] . Golnar Khodabndehloo, Mitra Mirhassani, Majid Ahmadi IEEE International Symposium on Multiple-Valued Logic . 2009

机译：16级电流模式多值动态存储器，具有增加的噪声裕度
5. Self-restored current-mode CMOS multiple-valued logic design and synthesis. [D] . Teng, Hsiang-Yung. 2003

机译：自恢复电流模式CMOS多值逻辑设计和综合。
6. Strange Attractors Generated by Multiple-Valued Static Memory Cell with Polynomial Approximation of Resonant Tunneling Diodes [O] . Jiri Petrzela 2018

机译：具有多项值静态存储器产生的奇怪吸引子具有谐振隧道二极管多项式近似
7. Energy-Aware Multiple-Valued Current-Mode Sequential Circuits Using a Completion-Detection Scheme [O] . Hirokatsu SHIRAHAMA, Takashi MATSUURA, Masanori NATSUI, 2010

机译：使用完成检测方案的能量感知多值电流模式顺序电路

16-level Current-Mode Multiple-Valued Dynamic Memory with Increased Noise Margin

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