Four-stage strategy has been confirmed to reduce the breakdown voltage of 70-nm impact-ionization MOS (I-MOS) devices. Simulation results showed that it was difficult to reduce the breakdown voltage below -5 V only by scaling down some device parameters such as LI, xj,se, and tox. Thus, a strained SOI (SSOI) substrate is introduced which has narrow EG. Though it consists of pure silicon, when strain is maximized, it is observed that the breakdown voltage reaches -1.25 V, which is much lower than that of GOI substrate.
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机译：已确认采用四阶段策略来降低70 nm碰撞电离MOS（I-MOS）器件的击穿电压。仿真结果表明，仅通过缩小某些器件参数（例如L I ，x j，se 和t < inf> ox 。因此，引入了应变的SOI（SSOI）基板，该基板的E G 较窄。尽管它由纯硅组成，但是当应变最大化时，可以观察到击穿电压达到-1.25 V，远低于GOI衬底的击穿电压。
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