From planar to vertical nanowires field-effect transistors

机译：从平面纳米线到垂直纳米线场效应晶体管

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The authors present the technological routes used to build planar and vertical gate all-around (GAA) field-effect transistors (FETs) using both Si and SiGe nanowires (NWs) and the electrical performances of the as-obtained components. Planar FETs are characterized in back gate configuration and exhibit good behavior such as an I_(on)/I_(off) ratio up to 10~6. Hysteretic behavior and sub-threshold slope values with respect to surface and oxide interface trap densities are discussed. Vertical devices using Si NWs show good characteristics at the state of the art with I_(on)/I_(off) ratio close to 10~6 and sub-threshold slope around 125 mV/decade while vertical SiGe devices also obtained with the same technological processes, present an I_(on)/I_(off) ratio from 10~3 to 10~4 but with poor dynamics which can be explained by the high interface traps density.

机译：作者介绍了使用Si和SiGe纳米线（NW）来构建平面和垂直栅极全能（GAA）场效应晶体管（FET）的技术路线以及所获得组件的电性能。平面FET以背栅配置为特征，并具有良好的性能，例如I_（on）/ I_（off）比率高达10〜6。讨论了相对于表面和氧化物界面陷阱密度的磁滞行为和亚阈值斜率值。使用Si NW的垂直器件在现有技术中表现出良好的特性，I_（on）/ I_（off）比率接近10〜6，亚阈值斜率约为125 mV /十倍，而垂直SiGe器件也采用相同的技术获得I_（on）/ I_（off）比率从10〜3到10〜4，但是动力学较差，这可以通过高界面陷阱密度来解释。

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《Nanowires and nanotubes - synthesis, properties, devices and energy applications of one-dimensional materials》|2012年|101-107|共7页
会议地点 San Francisco CA(US);San Francisco CA(US);San Francisco CA(US)
作者
Guitlaume Rosaz; Bassem Salem; Nicolas Pauc; Pascal Gentile; Priyanka Periwal; AlexisPotie; Thierry Baron; L. Latu-Romain; S. David;
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Laboratoire des Technologies de la Microelectronique (LTM) - UMR 5129 CNRS-UJF, CEA Grenoble, 17 Rue des Martyrs, F-38054 Grenoble, France,CEA, INAC/SP2M, Laboratoire SiNaPS, F-38054 Grenoble, France;

Laboratoire des Technologies de la Microelectronique (LTM) - UMR 5129 CNRS-UJF, CEA Grenoble, 17 Rue des Martyrs, F-38054 Grenoble, France;

CEA, INAC/SP2M, Laboratoire SiNaPS, F-38054 Grenoble, France;

CEA, INAC/SP2M, Laboratoire SiNaPS, F-38054 Grenoble, France;

Laboratoire des Technologies de la Microelectronique (LTM) - UMR 5129 CNRS-UJF, CEA Grenoble, 17 Rue des Martyrs, F-38054 Grenoble, France;

Laboratoire des Technologies de la Microelectronique (LTM) - UMR 5129 CNRS-UJF, CEA Grenoble, 17 Rue des Martyrs, F-38054 Grenoble, France;

Laboratoire des Technologies de la Microelectronique (LTM) - UMR 5129 CNRS-UJF, CEA Grenoble, 17 Rue des Martyrs, F-38054 Grenoble, France;

Laboratoire des Technologies de la Microelectronique (LTM) - UMR 5129 CNRS-UJF, CEA Grenoble, 17 Rue des Martyrs, F-38054 Grenoble, France;

Laboratoire des Technologies de la Microelectronique (LTM) - UMR 5129 CNRS-UJF, CEA Grenoble, 17 Rue des Martyrs, F-38054 Grenoble, France;

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From planar to vertical nanowires field-effect transistors

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