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Energy-Aware Hardware Implementation of Network Coding

机译：网络编码的节能型硬件实现

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In the last few years, Network Coding (NC) has been shown to provide several advantages, both in theory and in practice. However, its applicability to battery-operated systems under strict power constraints has not been proven yet, since most implementations are based on high-end CPUs and GPUs. This work represents the first effort to bridge NC theory with real-world, low-power applications. In this paper, we provide a detailed analysis on the energy consumption of NC, based on VLSI design measurements, and an approach for specifying optimal algorithmic parameters, such as field size, minimizing the required energy for both transmission and coding of data. Our custom, energy-aware NC accelerator proves the feasibility of incorporating NC into modern, low-power systems; the proposed architecture achieves a coding throughput of 80MB/s (60MB/s), while consuming 22uW (12.5mW) for the encoding (decoding) process.
机译：在过去的几年中，网络编码（NC）已显示出在理论上和实践上均具有许多优势。但是，由于大多数实现均基于高端CPU和GPU，因此尚未证明其在严格的功率约束下可适用于电池操作系统。这项工作代表了将NC理论与实际的低功耗应用联系起来的第一项努力。在本文中，我们基于VLSI设计测量结果，对NC的能耗进行了详细分析，并提供了一种用于指定最佳算法参数（例如字段大小）的方法，该方法可最大程度地减少数据传输和编码所需的能量。我们定制的节能型NC加速器证明了将NC集成到现代低功耗系统中的可行性。所提出的架构实现了80MB / s（60MB / s）的编码吞吐量，而编码（解码）过程则消耗22uW（12.5mW）。

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