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Design of a Family of VLSI High Speed Fuzzy Processors for Trigger Applications in HEPE

机译：HEPE触发应用的VLSI高速模糊处理器系列设计

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摘要

This paper describes the architecture of two VLSI Fuzzy chips designed to run at very high speed: 50 Mega Fuzzy Inference per Second (MFIPS) at least. The two projects differ in the number of inputs: one processes 2-4 seven bit inputs while the other one 10 inputs, each one ten bits. The two chips have been designed for applications in High Energy Physics Experiments (HEPE) where the apparatus, called trigger, needs to discriminate or preprocess different nuclear events in less than 1 microsecond. So far most of the fuzzy logic applications do not require high speed because not required by the industrial applications, therefore for HEPE was necessary the VLSI design of high speed fuzzy chips. In the first phase of our research 1.0 μm VLSI fuzzy chip [1], [2] prototype with four 7 bit inputs and one output running at 50 MFIPS was designed and constructed whose processing rate depends upon the number of rules of the fuzzy system. To further increase the speed we have faced the problem of processing, when possible, only the active fuzzy rules which are a few percent of the total ones. The research carried out on this prototype allowed us to extract some general conclusions:rn1. for applications with no more than 4 inputs and seven Membership Functions for each input only the active rules are processed. Our design has a processing rate of 320 ns for 4 inputs, whichever is the fuzzy system;rn2.for applications which need 10 inputs we plan to process a fuzzy system obtained by a Genetic Rule Generator [3], Such a fuzzy system is made of few rules, for our applications less than 60 rules. The processing rate is 20 ns time the number of rules.rnThe chips have been designed in 0.7 μm CMOS technology with ES2 foundry standard cells, the first has been already constructed and successfully tested while the second one is in design phase.
机译：本文介绍了设计用于以极高速度运行的两个VLSI Fuzzy芯片的体系结构：至少每秒50兆模糊推理（MFIPS）。这两个项目的输入数量不同：一个处理2-4个7位输入，而另一个处理10个输入，每个处理10位。这两款芯片是专为高能物理实验（HEPE）中的应用而设计的，该设备称为触发装置，需要在不到1微秒的时间内辨别或预处理不同的核事件。到目前为止，大多数模糊逻辑应用由于工业应用不需要而不需要高速，因此对于HEPE来说，高速模糊芯片的VLSI设计是必需的。在我们研究的第一阶段，设计并构建了具有4个7位输入和一个以50 MFIPS运行的输出的1.0μmVLSI模糊芯片[1]，[2]原型，其处理速度取决于模糊系统的规则数量。为了进一步提高速度，我们遇到了处理问题，在可能的情况下，仅主动模糊规则占总数的百分之几。在此原型上进行的研究使我们能够得出一些一般性结论：rn1。对于输入不超过4个且每个输入具有七个成员资格功能的应用程序，仅处理活动规则。我们的设计对4个输入的处理速度为320 ns，以模糊系统为准；对于需要10个输入的应用，我们计划处理由遗传规则生成器[3]获得的模糊系统，很少的规则，对于我们的应用程序，少于60条规则。处理速度是规则数量的20ns。rn该芯片采用0.7μmCMOS技术进行设计，并带有ES2铸造标准单元，其中第一个已经构建并成功测试，而第二个处于设计阶段。

著录项

  • 来源
    《New trends in fuzzy logic II》|1997年|172-179|共8页
  • 会议地点 Bari(IT)
  • 作者

    D. FALCHIERI; A. GABRIELLI; E. GANDOLFI; M. MASETTI; G.V. RUSSO; D. LO PRESTI; S. PANEBIANCO; C. PETTA; N. RANDAZZO; S. REITO; M. RUSSO; C. CALIGERI;

  • 作者单位

    Department of Physics, University of Bologna and INFN Section;

    Department of Physics, University of Bologna and INFN Section;

    Department of Physics, University of Bologna and INFN Section;

    Department of Physics, University of Bologna and INFN Section;

    Department of Physics, University of Catania and INFN Section;

    Department of Physics, University of Catania and INFN Section;

    Department of Physics, University of Catania and INFN Section;

    Department of Physics, University of Catania and INFN Section;

    Department of Physics, University of Catania and INFN Section;

    Department of Physics, University of Catania and INFN Section;

    Istituto di Ing. El. e Telecom. dell'Universita e and INFN Section of Catania;

    Centra Siciliano di Fisica Nucleare e Struttura della Materia e INFN Section of Catania;

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  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 模糊数学;
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