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Generic VHDL implementation of a PCNN with loadable coefficients

机译：具有可加载系数的PCNN的通用VHDL实现

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Abstract: This paper presents a general VHDL implementation of a Pulse Coupled Neural Network. The VHDL implementation is targeted for FPGA but can also be used with advantage for ASIC implementations. This particular case deals with images of the size 128 $MUL 128 pixels coming at a rate of 60 images per second, each image iterated by the PCNN 70 times, i.e. a real time image processing system. Thanks to the generality, this suggested solution can easily be transformed into, e.g., a solution with images sized 32 $MUL 32 pixels, coming at a speed of 960 images per second, assuming the same iteration length. The hardware requirement and problems are analyzed and solutions are proposed. Some problems that are dealt with are: the huge amount of data produced, the high throughput (i.e. the rate of new data produced) and the loading of coefficients during runtime.!19
机译：摘要：本文介绍了脉冲耦合神经网络的通用VHDL实现。 VHDL实现针对FPGA，但也可用于ASIC实现。该特定情况处理大小为128 $ MUL 128像素的图像，其速率为每秒60张图像，每个图像由PCNN迭代70次，即实时图像处理系统。由于通用性，此建议的解决方案可以轻松地转换为例如图像大小为32 $ MUL 32像素的解决方案，假设迭代长度相同，则每秒可以处理960张图像。分析了硬件需求和问题，并提出了解决方案。需要解决的一些问题是：产生大量数据，高吞吐量（即产生新数据的速率）以及运行时加载系数!! 19

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