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Effective model-based SRAF placement for full chip 2D layouts

机译：有效的基于模型的SRAF布局，可实现全芯片2D布局

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摘要

Traditional SRAF placement has been governed by a generation of rules that are experimentally derived based on measurements on test patterns for various exposure conditions. But with the shrinking technology nodes, there are increased challenges in coming up with these rules. Model-based SRAF placement can help in improved overall process window, with less effort. This is true especially for two-dimensional layouts, where SRAF placement conflicts can provide a formidable challenge with varying patterns and sources. This paper investigates the trade-offs and benefits of using model-based SRAF placement over rule-based for various design configurations on a full chip. The impact on cost, time, process-window and performance will be studied. This paper will also explore the benefits and limitations of more complex free-form SRAF and OPC shapes generated by Inverse Lithography Technology (ILT), and strategies for integration into a manufacturable mask.
机译：传统的SRAF放置受到一系列规则的支配，这些规则是根据各种曝光条件下测试图案的测量值通过实验得出的。但是随着技术节点的减少，提出这些规则的挑战越来越大。基于模型的SRAF放置可以帮助您以更少的精力改善整个过程窗口。对于二维布局尤其如此，SRAF放置冲突可能会在模式和来源不同的情况下带来巨大挑战。本文针对全芯片上的各种设计配置，研究了基于模型的SRAF布局与基于规则的布局之间的权衡和收益。将研究对成本，时间，过程窗口和性能的影响。本文还将探讨反光刻技术（ILT）生成的更复杂的自由形式SRAF和OPC形状的优点和局限性，以及集成到可制造掩模中的策略。

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