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首页> 外文会议>Optoelectronic interconnects and component integration XI >Photonic Switching for Reliable Nanoscale Three-Dimensional Integrated Network-On-Chips
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Photonic Switching for Reliable Nanoscale Three-Dimensional Integrated Network-On-Chips

机译：可靠的纳米级三维集成片上网络的光子交换

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摘要

As the multi-core architecture is becoming a prevailing high-performance chip design approach, power efficiency, limited bandwidth and low reliability have been recognized as major communication bottlenecks for on-chip networks (NOCs). To simultaneously tackle the above problems, we propose a three-dimensional integrated (3D1) photonic NOC architecture. This architecture is composed of the following layers: (i) the multi-core processor layer that host multiple heterogeneous processing cores together with corresponding local memories and network interfaces, (ii) multiple 3D memory layers that provide the bulk of on-chip memory, and (iii) photonic NOC layer. The photonic NOC layer is based on the optical cross-point switches (OXSs) implemented using active vertical coupler (AVC) structures. The use of this photonic NOC layer will provide ample bandwidth at reduced latencies along with low power consumption. The nanoscale photonic NOCs are sensitive to process variation and reliability issues. To deal with these problems, we proposed the use of LDPC codes with decoding based on simple majority-logic.
机译：随着多核体系结构成为一种流行的高性能芯片设计方法，功率效率，有限的带宽和低可靠性已被视为片上网络（NOC）的主要通信瓶颈。为了同时解决上述问题，我们提出了一种三维集成（3D1）光子NOC架构。该体系结构由以下几层组成：（i）承载多个异构处理核心以及相应的本地存储器和网络接口的多核处理器层，（ii）提供大量片上存储器的多个3D存储器层， （iii）光子NOC层。光子NOC层基于使用有源垂直耦合器（AVC）结构实现的光学交叉点开关（OXS）。该光子NOC层的使用将在减少延迟的同时提供足够的带宽以及低功耗。纳米级光子NOC对工艺变化和可靠性问题敏感。为了解决这些问题，我们提出了基于简单多数逻辑的带解码的LDPC码的使用。

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