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首页> 外文会议>Photonics, Devices, and Systems III >Two different ways for waveguides and optoelectronics components on top of C-MOS
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Two different ways for waveguides and optoelectronics components on top of C-MOS

机译：C-MOS顶部的波导和光电组件的两种不同方式

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While fabrication of photonic components at the wafer level is a long standing goal of integrated optics, new applications such as optical interconnects are introducing new challenges for waveguides and optoelectronic component fabrication. Indeed, global interconnects are expected to face severe limitations in the near future. To face this problem, optical links on top of a CMOS circuits could be an alternative. The critical points to perform an optical link on a chip are firstly the realization of compact passive optical distribution and secondly the report of optoelectronic components for the sources and detectors. This paper presents two different approaches for the integration of both waveguides and optoelectronic components. In a first "total bonding" approach, waveguides have been elaborated using classical "Silicon On Insulators " technology and then reported using molecular bonding on top off Si wafers. The SOI substrate was then chemically etched, after what InP dies were moleculary bonded on top of the waveguides. With this approach, optical components with low loses and a good equilibrium are demonsrated. Using molecular bonding, InP dies were reported with no degradation of the optoelectronic properties of the films. In a second approach, using PECVD silicon nitride or amorphous silicon coupled to PECVD silicon oxide, basic optical components are demonstrated. This low temperature technology is compatible with a microelectronic Back End process, allowing an integration of the waveguides directly on top of CMOS circuits. InP dies can then be bonded on top of the waveguides.
机译：虽然在晶片级制造光子组件是集成光学的长期目标，但诸如光互连之类的新应用正在为波导和光电组件制造带来新挑战。确实，在不久的将来，全球互连将面临严峻的局限。为了解决这个问题，可以选择在CMOS电路顶部的光链路。在芯片上执行光链路的关键点是首先实现紧凑的无源光分布，其次是用于源和检测器的光电组件的报告。本文提出了两种不同的波导和光电组件集成方法。在第一种“全键合”方法中，已经使用经典的“绝缘体上硅”技术对波导进行了详细说明，然后报道了在顶部硅晶片上使用分子键合的方法。然后将InP裸片分子键合在波导顶部后，对SOI衬底进行化学蚀刻。通过这种方法，损耗低且平衡良好的光学组件被去除了。据报道，使用分子键合InP芯片不会降低薄膜的光电性能。在第二种方法中，使用耦合到PECVD氧化硅的PECVD氮化硅或非晶硅，演示了基本光学组件。这项低温技术与微电子后端工艺兼容，可以将波导直接集成在CMOS电路的顶部。然后可以将InP裸片粘合在波导的顶部。

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