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Optimizing address code generation for array-intensive DSP applications

机译：针对阵列密集型DSP应用优化地址代码生成

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摘要

The application code size is a critical design factor for many embedded systems. Unfortunately, most available compilers optimize primarily for speed of execution rather than code density. As a result, the compiler-generated code can be much larger than necessary. In particular, in the DSP domain, the past research found that optimizing address code generation can be very important since address code can account for over 50% of all program bits. This paper presents a compiler-directed scheme to minimize the number of instructions to be generated to manipulate address registers found in DSP architectures. As opposed to most of the prior techniques that attempt to reduce the number of such instructions through careful address register assignment, this paper proposes modifying loop access patterns in array-intensive signal processing applications. In addition, it demonstrates how the proposed scheme can cooperate with a data layout optimizer for increasing its benefits further. We also discuss how optimizations that target effective address code generation can conflict with data locality-enhancing transformations. We evaluate the proposed approach using twelve array-intensive embedded applications. Our experimental results indicate that the proposed approach not only leads to significant reductions in code size but also outperforms prior efforts on reducing code size of array-intensive DSP applications.
机译：对于许多嵌入式系统来说，应用程序代码的大小是至关重要的设计因素。不幸的是，大多数可用的编译器主要针对执行速度而不是代码密度进行优化。结果，编译器生成的代码可能比必要的大得多。特别是在DSP领域，过去的研究发现优化地址代码的生成非常重要，因为地址代码可以占所有程序位的50％以上。本文提出了一种面向编译器的方案，以最大程度地减少生成用于操纵DSP体系结构中的地址寄存器的指令数量。与大多数尝试通过仔细的地址寄存器分配减少此类指令数量的现有技术相反，本文提出了在阵列密集型信号处理应用中修改循环访问模式的建议。此外，它演示了所提出的方案如何与数据布局优化器配合以进一步提高其收益。我们还将讨论针对有效地址代码生成的优化如何与数据局部性增强转换冲突。我们使用十二个阵列密集型嵌入式应用程序评估提出的方法。我们的实验结果表明，所提出的方法不仅可以导致代码大小的显着减少，而且在减少数组密集型DSP应用程序的代码大小方面也胜过先前的努力。

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