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首页> 外文会议>Proceedings of the 19th annual symposium on Integrated circuits and systems design >Low maintenance verification
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Low maintenance verification

机译：低维护验证

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The verification of modern computing systems has grown to dominate the cost of system design, often with limited success, as designs continue to be released with latent bugs. This trend is accelerated by the advent of highly integrated system-on-a-chip (SoC) designs, which feature multiple complex subcomponents connected by simultaneously active interfaces. To cope with this challenge, logic simulation techniques are predominant in the industry, however, the coverage of the tests generated is usually low, with the result that even months of simulation provide little confidence in the correctness of the design. Additionally, these traditional techniques require a lot of effort from the engineering team to direct the verification activity towards specific design areas of critical quality. Nonetheless, they have such high inertia in existing development processes that the cost to transition to alternative methodologies, such as formal techniques, is high.This talk will introduce a new generation of hybrid verification solutions, which we call "Low Maintenance Verification", where the contribution of formal techniques is transparently deployed within a simulation-based verification framework. Our use of formal techniques in this context greatly enhances the level of automation of the verification process, by generating solutions which can focus on a verification goal with minimal guidance from the engineer. We will overview some of the techniques that we developed in this space, including Guido and StressTest, two solutions that can automatically generate "interesting" verification scenarios. Our preliminary experience in the domain of low maintenance verification indicates that this family of techniques can effectively lead to high-performance, high-coverage verification solutions, by generating concise error traces with minimal demands on verification engineers and no change in the verification process.
机译：随着设计继续带有潜在的错误发布，现代计算系统的验证已逐渐占据系统设计成本的主导地位，但通常收效甚微。高度集成的片上系统（SoC）设计的出现加快了这种趋势，该设计具有多个同时通过活动接口连接的复杂子组件。为了应对这一挑战，逻辑仿真技术在业界占主导地位，但是，生成的测试的覆盖率通常很低，结果，甚至数月的仿真对设计的正确性也缺乏信心。此外，这些传统技术需要工程团队付出大量努力才能将验证活动引导至关键质量的特定设计领域。尽管如此，他们在现有的开发过程中惯性很高，以至于过渡到替代方法（例如正式技术）的成本很高。本讲座将介绍新一代的混合验证解决方案，我们称之为“低维护验证”，其中形式技术的贡献透明地部署在基于模拟的验证框架中。在这种情况下，我们使用形式化技术，通过生成可以集中于验证目标的解决方案，而无需工程师的指导，大大提高了验证过程的自动化水平。我们将概述我们在该领域开发的一些技术，包括Guido和StressTest，这两种解决方案可以自动生成“有趣的”验证方案。我们在低维护验证领域的初步经验表明，该系列技术可以通过生成简明的错误跟踪信息，而对验证工程师的要求最低，而无需更改验证过程，从而可以有效地提供高性能，高覆盖率的验证解决方案。

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